IBM 5150 - Page 40

DO-D7
I/O
Data Bits 0 to 7: These lines provide
data bus bits 0 to 7 for the
microprocessor, memory, and
1/0
devices. DO is the least significant bit
(LSB) and D7 is the most significant bit
(MSB). These lines are active high.
r"'\
-DACKO
to
0
-DMA Acknowledge 0 to 3: These lines
-DACK3
are used to acknowledge DMA requests
(DRQI-DRQ3) and refresh system
dynamic memory (-DACKO). They are
active low.
DRQ1-DRQ3
I DMA Request 1 to 3: These lines are
asynchronous channel requests used
by
peripheral devices to gain DMA service.
They are prioritized with DRQ3 being
the lowest and DRQl being the highest.
A request
is generated by bringing a
DRQ line to an active level (high). A
DRQ line must be held high until the
corresponding
DACK line goes active.
~
-I/O CU CK I
- II 0 Channel Check: This line
provides the microprocessor with parity
(error) information
on memory or
devices in the I/O channel. When this
signal
is active low, a parity error is
indicated.
I/O CURDY I
I/O Channel Ready: This line,
normally high (ready), is pulled low (not
ready) by a memory or 110 device to
lengthen
I/O or memory cycles. It
allows slower devices to attach to the
1/0 channel with a minimum of
difficulty. Any slow device using this
line should drive it low immediately
upon detecting a valid address and a
Read or Write command. This line
should never
be held low longer than 10
System Board
1-21