I/O
Channel
The
I/O
channel
is
an
extension of the 8088 microprocessor bus.
It is, however, demultiplexed, repowered, and enhanced by the
addition
of
interrupts and direct memory access (DMA)
functions.
The
I/O
channel contains an 8-bit, bidirectional data bus, 20
address lines, 6 levels of interrupt, control lines for memory and
I/O
read
or
write, clock and timing lines, 3 channels
of
DMA
control lines, memory refresh-timing control lines, a 'channel
check' line, and power and ground for
the
adapters.
Four
voltage
levels are provided for
I/O
cards:
+5
Vdc ±
5%,
-5 Vdc ±
10%,
+12 Vdc ±
5%,
and -12 Vdc ±
10%.
These functions are
provided in a 62-pin connector with 100-mil card tab spacing.
An
'I/O
channel ready' line
(I/O
CH
RDY)
is
available
on
the
I/O
channel to allow operation with slow
I/O
or
memory devices.
These devices can pull
I/O
CH
RDY low to add wait states to the
following operations:
• Normal memory read and write cycles take four 210ns clocks
for a cycle time of
840ns/byte.
• Microprocessor-generated
I/O
read and write cycles require
five clocks for a cycle time of 1.05,us/byte.
•
DMA
transfers require five clocks for a cycle time
of
1.05,us/byte.
I/O
devices are addressed using
I/O
mapped address space. The
channel
is
designed so that 768
I/O
device addresses are available
to the
I/O
channel cards.
A
'channel
check' line exists for reporting error conditiol1S to the
microprocessor. Activating this line results in a non-maskable
interrupt (NMI) to the 8088 microprocessor. Memory expansion
options use this line to report parity errors.
The
I/O
channel
is
repowered to provide sufficient drive' to power
all eight (J1 through J8) expansion slots, assuming two low-power
System Board 1-15
To Next Page
Loading...
Need help?
General
