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I/O

Channel Description

The following

a description of the

I/O

Channel. All lines are

TTL-compatible.

AO-A19

(0)

Address bits 0 to 19: These lines are used to address memory and

I/O

devices within the system. The 20 address lines allow access

of up to 1M byte of memory.

the least significant bit (LSB)

and A19

the most significant bit (MSB). These lines are

generated by either the microprocessor

DMA controller. They

are active high.

AEN

(0)

Address Enable: This line

used to de-gate the microprocessor

and other devices from the

I/O

channel to allow

DMA

transfers

to take place. When this line

active (high), the

DMA

controller

has control of the address bus, data bus, Read command lines

(memory and

I/O),

and the Write command lines (memory and

I/O).

ALE

(0)

Address Latch Enable: This line

provided by the 8288 Bus

Controller and

used

the system board to latch valid

addresses from the microprocessor. It

available to the

I/O

channel as an indicator of a valid microprocessor address (when

used with AEN). Microprocessor addresses are latched with the

falling edge of ALE.

1-20 System Board

Brand	IBM
Model	XT 5160
Category	Desktop
Language	English

IBM XT 5160 User Manual

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IBM XT 5160 Specifications

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