3-2-3
MULTIPLIER
AND
DRIVER CIRCUITS
1.
VHP Circuit
The
RF signal from the PLL UNIT
is amplified
by
IC1
on the
VHF PA UNIT
to obtain 25W, and the
output
from
pin 4 on
IC1 is fed to the ANT switching
circuit. In the transmit mode
D2 and D4 in the T/R switching circuit
are turned ON, and
L2
and
C2 become a parallel resonant circuit. The
output power
from pin 4 on IC1 is fed
to the antenna terminal through the
bandpass filter.
2. UHF Circuit
The RF signal
from the PLL UNIT is amplified
by IC2 on the
UHF PA UNIT
to obtain 25W, and the
output
from
pin 5 on
IC2
is
fed to the ANT switching circuit. In
the transmit mode,
D5 and D7 in
the
T/R
switching circuit are turned
ON, and
LI 5 and
C41 become a parallel resonant circuit. The
output
power from pin
5 on IC2 is fed to the antenna
terminal
through the
bandpass filter.
3. VHF/UHF
ALC (Automatic Levei Control) Circuit
(PA UNiTS AND MAIN UNIT)
This circuit stabilizes the output
power
even
when the power
supply voltage or the antenna impedance is fluctuating. The
varying current from the
power
amplifier
at R1
(VHF) and R6
and R1
1
(UHF)
is
amplified
by the
IC2B
(VHF) or
IC2A (UHF)
differential
amplifiers on the MAIN UNIT.
The
output
voltage
is fed
to
01
(VHF) or
03
(UHF) which
control
the current to
the module’s driver
stage, maintaining constant
RF
power.
4. VHF/UHF RF Meter
Circuit
(PA UNITS AND MAIN UNIT)
A sample of the RF
output power is fed to D3 (VHF) or D6
(UHF) through
09
(VHF) or
027
(UHF), is rectified, and is
passed to
the
module’s driver stage to maintain constant RF
power.
5. Power Supply Circuit (MAIN UNIT)
The
13.8V
from
the DC connector is applied
to
104
on
the
MAIN UNIT through filters
consisting of L22,
097,
and R89.
This
causes
9V
to be
fed
to the MAIN and PLL-YGR UNITS.
3-3
PLL (PHASE-LOCKED
LOOP)
CIRCUITS
3-3-1
PLL
The
PLL
is
designed so that the desired frequency
is
generated directly
by the VCO using a dual modulation
prescaler
system, and is composed of the IC2
prescaler IC
and the IC1 PLL 10. The PLL circuit is fed
“divided-by-N”
DATA
from the CPU to determine the operating
frequency.
N-DATA is the ratio of the desired frequency
(the transmit
frequency in transmit
mode
and
the
first
local oscillator
frequency in receive mode) and the reference frequency.
_
Desired frequency
Reference frequency
Crystal XI oscillates in Q1 and its output signal
is
divided
by
a dividing circuit in 101 that obtains a reference frequency of
5kHz for the IC-3200A (6.25kHz for the IC-3200E version).
The signal from
the VCO that is buffer-amplified
at
Q6
is
divided N times
at
102
and
101
. The signal inside 101
is phase
detected and
the detected
signal
is output from pin 1
1
on
101. The
output
signal is applied
to the TX D1 and TX D2
varactor diodes (or RX D1 and RX D2) in the VCO
and
is
passed through the
Q2-Q3
loop filter
to
control
the VCO
frequency.
3-3-2
VCO/FM MODULATION CIRCUITS
The
VCO is composed of the following circuits: VHF RX,
UHF RX, VHF TX, and UHF TX. A PD signal from the PLL
is
fed
to
the
varactor diode connected to each drain of the
FETs
to control the VCO
frequency.
1. Dual
Modulus Prescaler
102 is a dual modulus prescaler that divides the signal
generated
by
the VCO
by
either 64
or 65.
The VHF
receive
range is 102.125~119.125MHz
and the transmit range is
140.00—
1
50.00MHz.
The
UHF receive range is
409.
125—
419. 125MHz and
the
transmit range
is
440.00—
450.00MHz. 101 is a CMOS LSI chip designed for
use as a
frequency synthesizer.
It incorporates a 6-bit
swallow counter, an
11
-bit programmable counter,
a phase
comparator, a charge pump, and a frequency divider for
the
reference frequency. The reference frequency from
Q1 is fed
to pin 15 on 101. Here the frequency
is
divided
by
1024,
the
reference frequency
becomes
5kHz (6.25kHz for the
IC-3200E
version), and the frequency is fed to
pin
2 on
101
.
2. VHF/UHF RX VCO Circuit
The RX VCO is a Clapp oscillator circuit which oscillates in
the VHF range
107.125—
119.125MHz
or
in
the
UHF
range
409.125—
419.125MHz.
The
frequency
is controlled by the
DC
voltage from
VRXC on 103. The drains of
01
(VHF) and
Q4
(UHF)
receive a positive 9V while the tranceiver is in the
receive mode and
02
(VHF) or
04
(UHF)
are turned ON.
Thus
the
frequency
is
generated
when
the
FET source is at
ground level.
3. VHF/UHF TX VCO
Circuit
The TX
VCO is a Clapp oscillator circuit. The frequency
is
controlled
by
the DC voltage from V-VCO-C or
U-VCO-C
from IC3. When the drains of
06
(VHF) or
03
(UHF) receives
positive 9V,
04
(VHF)
or
03
(UHF) turns ON. The VHF
oscillator frequency
(140—
150MHz) is fed out through
C17
and the UHF oscillator frequency (440—
450MHz) is fed
out
through the
02
multiplier amplifier.
4. Low-pass Filter Circuit
The local
oscillator signal from the RX VCO
(VHF:
102.125—
119.125,
UHF:
409.125MHz)
is
divided by 2
by
the
02 multiplier amplifier. The VHF local oscillator signal is fed
to J2 on the MAIN UNIT through D13 and a low-pass filter
consisting of L12, L13,
C99, C100
and
C101.
The UHF local
oscillator signal is fed to
J4
on the MAIN UNIT through D12
and a
low-pass
filter consisting of L10, L11,
C94, C95,
and
C96.
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