IDT VersaClock 3S - Single-ended Output Termination; Termination for Single-ended Output 1 (SE_1)

11©2017 Integrated Device Technology, Inc. June 8, 2017
VersaClock
®
3S - 5P35023 Evaluation Board User Manual
Note: **The differential output is applicable to LPHCSL which is the default configuration of the board.
*The single-ended output is applicable to LVCMOS which is the default configuration of the board.
Contact IDT if user wants to change termination configuration to support other output signal types.
Ordering Information
Table 8. Termination for Single-ended Output 2 (SE_2)
Signal Type Series Resistor: R2 Series Capacitors: C17
*LVCMOS 33Ω Not installed
Table 9. Termination for Single-ended Output 3 (SE_3)
Signal Type Series Resistor: R3 Series Capacitors: C18
*LVCMOS 33Ω Not installed
Table 10. Termination for Single-ended REF Output (REF)
Signal Type Series Resistor: R4 Series Capacitors: C15
*LVCMOS 33Ω Not installed
Table 11. Termination for Differential and Single-ended Clock Input (CLKIN\CLKINB)
Signal Type Series Resistor: R8 Series Resistor: R15
Differential Clock Input Not installed Not installed
Single-ended Clock Input Not installed Not installed
Table 12. Orderable Part Number
Part Number Description
EVK5P35023 Evaluation board with all differential outputs terminated as LPHCSL; single-ended terminated as LVCMOS.