Integra DHC-80.2 Service Manual

CS_PLD
LRCK4
BC4K
RMCK
PCMCSW1/DSDSW PCMSUR1/DSDC
PCMSB1/DSDSRPCMSB1/DSDSR
DSDSL
PCMLRCK/DSDFR
HDMI_MCK
PCMBCK/DSDCLK PCMF/DSDFL
MCK
LRCK4
BCK4
PCM_FR/RLRW4
PCM_FL/LHLW4
PCM_SWL/SWR4
PCM_SR/SBR4
PCM_C4
PCM_SL/SBL4 // PCMF4PCMF2
PCMSUR2
PCMCSW2
PCMSB2
LRCK2
BCK2
MCK
PCMSUR3
PCMCSW3
PCMSB3
PCMHW3
PCMSWR3
LRCK3
BCK3
PCMF3
DIGCLK
DIGSDO
DIR
ADC
ADC
+6dB
+6dB
VLSC2
+6dB
VLSC2
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
VLSC2
+6dB
SW/SW to FR
SW/SW to FL
SW
SBR
SR
RH
FR
C
C
LH
FL
SBL
SL
VOLUME
3-3-2 x2
analog
ASP BLOCK
MIC
MIC AMP
3V->5V
HDMI_SPDIF
IN1
IN2
(HDMI)
(CODEC)
SW1
x4
CODEC
HDMI H
L
OUT
SEL0
SEL0
analog
PCM
DSD
x14
DSD
PCM
OUT
H
L
XX
PCM_DSP LH
HL
ALL CH STE
PCM_DIRECT
OUT
LL
HH
PCM_DSP
ALL CH STE
PCM_DIRECT
OUT
SW2
SW3
DSP_BCK
DSP_SL/SBL
DSP_C
DSP_LRCK
DSP_FL/LHLW
DSP_FR/RLRW
DSP_SR/SBR
DSP_SWL/SWR
DAC6DAC5DAC2DAC1 DAC3 DAC4
SEL1
SEL2
SEL2SEL1
SEL3
SEL3
FROM _3DSP
RMCK
2
3
4
5
6
7
1
8
9
x8
PCMF/DSDFL
PCMSUR/DSDC PCMCSW/DSDSW PCMSB/DSDSR
PCMLRCK/DSDFR PCMBCK/DSDCLK
PCMLRCK/DSDFR
MCK
HDMISPDIF/DSDSL
PCM/DSD toDSP
PCM_F3
TO HDMI TX
RX
FRONT
HDMI
RX
HDMI
TX
OUT2
OUT1
HDMI
TX
HDMI
TX
DSP1
DSP3(***)
DSP
DIG/NETUSB
48/44
DSP2(***)
(SWL/SWR)(SR/SBR)(FR/RchHW)(FL/LchHW)(SL/SBL) (C)
(FRONT IN)
OPT FRONT
OPT3
OPT2
OPT1
COAX 1
COAX 2
NET
COAX 3
TC74HC157FTx2
OPTSEL1_A
101112131415161718192021
242526
27
28
29
30
31
32
33
34
35363738
39 40 41 42
OPTSEL1_B OPTSEL1_C
IN1-?
23
22
PLL
Jitter Remover
DA83x
45
SW8
MCK or Ji.ReMCK
Jitter Re
MCK
OUT
MCK
JiRe_MCK H
L
or HARD SW
SEL10
SEL10
DIGITAL AUDIO CLOCK BLOCK
Schematic Diagram (PART-5)
Model No.TX-NR3008/NR5008/NA5008,
DTR-70.2/80.2,PR-SC5508,DHC-80.2
16
AINL-
15
AINL+
14
AINR+
13
AINR-
BCK/GND
SCK/BCK
LRCK/DATA_SW
DATA/DATA_C
BCK/GND
SCK/BCK
LRCK/DATA_FR
BCK/GND
SCK/BCK
DATA/DATA_SL
LRCK/DATA_SR
BCK/GND
SCK/BCK
DATA/DATA_SBL
LRCK/DATA_SBR
BCK/GND
SCK/BCK
DATA/DATA_CR
LRCK/DATA_SWR
BCK/GND
LRCK/DATA_FR
DATA/DATA_FL
SCK/BCK
DATA/DATA_FL
AXR0[4]1
AXR0[4]2
AXR0[1]
AXR0[2]
AXR0[3]
AXR0[4]
AXR0[0] ACLKX0
AFSX0
MCLK SCK/DCLK WS/DR0 SD0/DL0
SD1/DR1
SPDIF/DL2
SD3/DR2
SD2/DL1 SD0/DL1 SCK/DCLK1
WS/DR1
MCLK1
ACLKX0
AFSX0
AXR0[0]
AXR0[12]/AXR1[1]
AXR0[11]/AXR1[2]
AFSR0
ACLKR0
AXR0[1]
AXR0[2]
AXR0[3]
CLKIN
AHCLKX0/AHCLKX2
CLKIN
AXR0[3]
AXR0[2]
AXR0[1]
AXR0[0]
AFSX0
ACLKX0
AHCLKX0/AHCLKX2
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[15]/AXR2[0]
AXR0[14]/AXR2[1]
AXR0[13]/AXR1[0]
AXR0[12]/AXR1[1]
ACLKR0
AFSR0
AXR0[5]
AXR0[4]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR1[0]
AXR0[16]/AXR2[1]
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
AFSR0
ACLKR0
AHCLKX0/AHCLKX2
AXR0[12]/AXR1[1]
AXR0[11]/AXR1[2]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
ACLKX0
AFSX0
CLKIN
AXR0[4]
AXR0[5]
.
.
24.576MHz
1 2
12.288MHz
1 2
11.2896MHz
1 2
.
.
TX-NR3008/ 5008, TX-NA5008, DTR-70.2/ 80.2, PR-SC5508, DHC-80.2
SCHEMATIC DIAGRAMS-5
BLOCK DIAGRAM DIGITAL AUDIO SECTION
TX-NR3008/ 5008, TX-NA5008, DTR-70.2/ 80.2, PR-SC5508, DHC-80.2
A
1
2
3
4
5
BCDEF GH
6
7
8
IJK

Integra DHC-80.2 Specifications

General

Brand	Integra
Model	DHC-80.2
Category	Controller
Language	English