Intel 80960KB

80960KB
18
1. Clock rise and fall times are not tested.
2. A float condition occurs when the maximum output current becomes less than I
LO
. Float delay is not tested; however, it
should not be longer than the valid delay.
3. LAD31:0, BADAC
, HOLD, LOCK and READY are synchronous inputs. IAC/INT
0
, INT
1
, INT
2
/INT
R
and INT
3
may be syn-
chronous or asynchronous.
Table 8. 80960KB AC Characteristics (20 MHz)
Symbol Parameter Min Max Units Notes
Input Clock
T
1
Processor Clock Period (CLK2) 25 125 ns V
IN
= 1.5V
T
2
Processor Clock Low Time (CLK2) 6 ns V
IL
= 10% Point = 1.2V
T
3
Processor Clock High Time (CLK2) 6 ns V
IH
= 90% Point = 0.1V + 0.5 V
CC
T
4
Processor Clock Fall Time (CLK2) 10 ns V
IN
= 90% Point to 10% Point (1)
T
5
Processor Clock Rise Time (CLK2) 10 ns V
IN
= 10% Point to 90% Point (1)
Synchronous Outputs
T
6
Output Valid Delay 2 20 ns
T
6H
HLDA Output Valid Delay 4 23 ns
T
7
ALE Width 12 ns
T
8
ALE Output Valid Delay 2 18 ns
T
9
Output Float Delay 2 20 ns (2)
T
9H
HLDA Output Float Delay 4 20 ns (2)
Synchronous Inputs
T
10
Input Setup 1 3 ns (3)
T
11
Input Hold 5 ns (3)
T
11H
HOLD Input Hold 4 ns (3)
T
12
Input Setup 2 7 ns (3)
T
13
Setup to ALE Inactive 10 ns
T
14
Hold after ALE Inactive 8 ns
T
15
Reset Hold 3 ns
T
16
Reset Setup 5 ns
T
17
Reset Width 1025 ns 41 CLK2 Periods Minimum
NOTES: