Intel 80960KB

80960KB
20
Figure 15. Processor Clock Pulse (CLK2)
Figure 16. RESET Signal Timing
HIGH LEVEL (MIN) 0.55V
CC
LOW LEVEL (MAX) 0.8V
T
1
T
3
T
5
T
4
T
2
90%
10%
1.5 V
...
...
...
...
CLK2
CLK
RESET
OUTPUTS
FIRST
ABCDA
INIT PARAMETERS (BADAC
,
INT
0
/IAC) MUST BE SET UP 8 CLOCKS
PRIOR TO THIS CLK2 EDGE
INIT PARAMETERS MUST BE HELD
BEYOND THIS CLK2 EDGE
T
15
= RESET HOLD
T
16
= RESET SETUP
T
17
= RESET WIDTH
T
15
T
16
T
17