Intel Arria 10 series User Manual

Module Description
To apply the Quartus INI, include
“permit_nf_pll_reconfig_out_of_lock=on” in the quartus.ini file and
place in the file the Intel Quartus Prime project directory. You should see a
warning message when you edit the IOPLL reconfiguration block
(pll_hdmi_reconfig) in the Quartus Prime software with the INI.
Note:
Without this Quartus INI, IOPLL reconfiguration cannot be completed if
the IOPLL loses lock during reconfiguration.
PIO The parallel input/output (PIO) block functions as control, status and reset
interfaces to or from the CPU sub-system.
2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
15

Intel Arria 10 series Specifications

General

Family	Arria 10
Manufacturer	Intel
Transceiver Data Rate	Up to 17.4 Gbps
Core Voltage	0.9 V
Process Technology	20 nm
Category	FPGA
Package Options	FBGA
ALMs	42, 720 - 427, 200
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -55°C to +125°C (Extended)