Intel Arria 10 series User Manual

Figure 7. Multi-Rate Reconfiguration Sequence Flow
The figure illustrates the multi-rate reconfiguration sequence flow of the controller when it receivers input data
stream and reference clock frequency, or when the transceiver is unlocked.
Reset the RX HDMI PLL and RX transceiver.
Enable the rate detection circuit to measure incoming TMDS clock.
Accept acknowledgement with clock frequency band and desired
RX HDMI PLL and RX transceiver settings.
Determine if RX HDMI PLL and/or RX transceiver reconfiguration
is required based on the previous and current detected clock
frequency band and color depth. Different color depths may fall
within the same clock frequency band.
Request RX HDMI PLL and/or RX transceiver reconfiguration if the
previous and current clock frequency band or color depth differs.
The controller reconfigures the RX HDMI PLL and/or RX transceiver
(followed by recalibration on Intel Arria 10 device).
Reconfiguration Required
Reconfiguration
Not Required
When all reconfiguration processes complete or the previous and
current clock frequency band and color depth do not differ, reset
the RX HDMI PLL and RX transceiver.
Enable rate the detection circuit periodically to monitor the
reference clock frequency. If the clock frequency band changes or
the RX HDMI PLL or RX transceiver or HDMI core lose lock, repeat
the process.
Table 8. HDMI TX Top Components
Module Description
TX Core Top The TX Core top level consists of:
continued...
2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
16

Intel Arria 10 series Specifications

General

Family	Arria 10
Manufacturer	Intel
Transceiver Data Rate	Up to 17.4 Gbps
Core Voltage	0.9 V
Process Technology	20 nm
Category	FPGA
Package Options	FBGA
ALMs	42, 720 - 427, 200
Operating Temperature	0°C to +85°C (Commercial), -40°C to +100°C (Industrial), -55°C to +125°C (Extended)