Intel Arria 10 series User Manual

Control Signal
hdmi_tx_vsync
Input 1 HDMI TX Video Vsync. This
signal should be synchronized to
the link speed clock domain.
The core inserts the HDR
InfoFrame to the auxiliary
stream at the rising edge of this
signal.
Table 12. HDR Data Module (altera_hdmi_hdr_infoframe) Signals
Signal Direction Width Description
hb0
Output 8 Header byte 0 of the Dynamic
Range and Mastering
InfoFrame: InfoFrame type
code.
hb1
Output 8 Header byte 1 of the Dynamic
Range and Mastering
InfoFrame: InfoFrame version
number.
hb2
Output 8 Header byte 2 of the Dynamic
Range and Mastering
InfoFrame: Length of
InfoFrame.
pb
Input 224 Data byte of the Dynamic Range
and Mastering InfoFrame.
Table 13. Dynamic Range and Mastering InfoFrame Data Byte Bundle Bit-Fields
Bit-Field Definition Static Metadata Type 1
7:0 Data Byte 1: {5'h0, EOTF[2:0]}
15:8 Data Byte 2: {5'h0, Static_Metadata_Descriptor_ID[2:0]}
23:16 Data Byte 3: Static_Metadata_Descriptor display_primaries_x[0], LSB
31:24 Data Byte 4: Static_Metadata_Descriptor display_primaries_x[0], MSB
39:32 Data Byte 5: Static_Metadata_Descriptor display_primaries_y[0], LSB
47:40 Data Byte 6: Static_Metadata_Descriptor display_primaries_y[0], MSB
55:48 Data Byte 7: Static_Metadata_Descriptor display_primaries_x[1], LSB
63:56 Data Byte 8: Static_Metadata_Descriptor display_primaries_x[1], MSB
71:64 Data Byte 9: Static_Metadata_Descriptor display_primaries_y[1], LSB
79:72 Data Byte 10: Static_Metadata_Descriptor display_primaries_y[1], MSB
87:80 Data Byte 11: Static_Metadata_Descriptor display_primaries_x[2], LSB
95:88 Data Byte 12: Static_Metadata_Descriptor display_primaries_x[2], MSB
103:96 Data Byte 13: Static_Metadata_Descriptor display_primaries_y[2], LSB
111:104 Data Byte 14: Static_Metadata_Descriptor display_primaries_y[2], MSB
119:112 Data Byte 15: Static_Metadata_Descriptor white_point_x, LSB
127:120 Data Byte 16: Static_Metadata_Descriptor white_point_x, MSB
135:128 Data Byte 17: Static_Metadata_Descriptor white_point_y, LSB
continued...
2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
22

Intel Arria 10 series Specifications

General

Brand	Intel
Model	Arria 10 series
Category	Motherboard
Language	English