Intel Arria 10 series User Manual

HDMI FMC Daughter Card Pins on FMC Port B
fmcb_la_tx_p_10
Input 1 HDMI RX I
2
C SCL
fmcb_la_tx_p_12
Input 1 HDMI TX hot plug detect
fmcb_la_tx_n_12
Inout 1 HDMI I
2
C SDA
fmcb_la_rx_p_10
Inout 1 HDMI I
2
C SCL
Table 16. HDMI RX Top-Level Signals
Signal Direction Width Description
Clock and Reset Signals
mgmt_clk
Input 1 System clock input (100 MHz)
reset
Input 1 System reset input
tmds_clk_in
Input 1 HDMI RX TMDS clock
i2c_clk
Input 1 Clock input for DDC and SCDC interface
vid_clk_out
Output 1 Video clock output
ls_clk_out
Output 8 Link speed clock output
sys_init
Output 1 System initialization to reset the system
upon power-up
RX Transceiver and IOPLL Signals
rx_serial_data
Input 3 HDMI serial data to the RX Native PHY
gxb_rx_ready
Output 1 Indicates RX Native PHY is ready
gxb_rx_cal_busy_out
Output 3 RX Native PHY calibration busy to the
transceiver arbiter
gxb_rx_cal_busy_in
Input 3 Calibration busy signal from the
transceiver arbiter to the RX Native PHY
iopll_locked
Output 1 Indicate IOPLL is locked
gxb_reconfig_write
Input 3 Transceiver reconfiguration Avalon-MM
interface from the RX Native PHY to the
transceiver arbiter
gxb_reconfig_read
Input 3
gxb_reconfig_address
Input 30
gxb_reconfig_writedata
Input 96
gxb_reconfig_readdata
Output 96
gxb_reconfig_waitrequest
Output 3
RX Reconfiguration Management
rx_reconfig_en
Output 1 RX Reconfiguration enables signal
measure
Output 24 HDMI RX TMDS clock frequency
measurement (in 10 ms)
measure_valid
Output 1 Indicates the measure signal is valid
os
Output 1 Oversampling factor:
continued...
2 Intel FPGA HDMI Design Example Detailed Description
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
27

Intel Arria 10 series Specifications

General

Brand	Intel
Model	Arria 10 series
Category	Motherboard
Language	English