Intel Arria 10 series

Folders Files
reconfig_mgmt
/mr_compare_pll.v
/mr_compare_rx.v
/mr_rate_detect.v
/mr_reconfig_master_pll.v
/mr_reconfig_master_rx.v
/mr_reconfig_mgmt.v
/mr_rom_pll_dprioaddr.v
/mr_rom_pll_valuemask_8bpc.v
/mr_rom_pll_valuemask_10bpc.v
/mr_rom_pll_valuemask_12bpc.v
/mr_rom_pll_valuemask_16bpc.v
/mr_rom_rx_dprioaddr_bitmask.v
/mr_rom_rx_valuemask.v
/mr_state_machine.v
sdc
/a10_hdmi2.sdc
/mr.sdc
/jtag.sdc
Table 2. Generated Simulation Files
Folders Files
aldec
/aldec.do
/rivierapro_setup.tcl
cadence
/cds.lib
/hdl.var
/ncsim.sh
/ncsim_setup.sh
<cds_libs folder>
mentor
/mentor.do
/msim_setup.tcl
synopsys
/vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
/vcsmx/synopsys_sim_setup
continued...
1 Intel
®
FPGA HDMI Design Example Quick Start Guide for Intel
®
Arria
®
10 Devices
UG-20077 | 2017.11.06
Intel
®
FPGA HDMI Design Example User Guide for Intel
®
Arria 10 Devices
6