Summary Tables of Changes
16 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
as expected
N39 X X X X Fixed
Processor may Timeout Waiting for a
Device to Respond after ~0.67 Seconds
N40 X X X X X X X X No Fix
Cascading of Performance Counters
does not work Correctly when Forced
Overflow is Enabled
N41 X Fixed
Possible Machine Check Due to Line-
Split Loads with Page-Tables in
Uncacheable (UC) Space
N42 X X X X Fixed
IA32_MC1_STATUS MSR ADDRESS
VALID bit may be set when no Valid
Address is Available
N43 X X X X X X X X No Fix
EMON event counting of x87 loads may
not work as expected
N44 X X X X Fixed
Software controlled clock modulation
using a 12.5% or 25% duty cycle may
cause the processor to hang
N45 X X Fixed
Speculative page fault may cause
livelock
N46 X X Fixed
PAT index MSB may be calculated
incorrectly
N47 X X X Fixed
SQRTPD and SQRTSD may return
QNaN indefinite instead of negative
zero
N48 X X X X Fixed
Bus invalidate line requests that return
unexpected data may result in L1
cache corruption
N49 X X X X Fixed
Write Combining (WC) load may result
in unintended address on system bus
N50 X X X X X Fixed
Incorrect data may be returned when
page tables are in Write Combining
(WC) memory space
N51 X X X Fixed
Buffer on resistance may exceed
specification
N52 X X X X X X X X No Fix
Processor issues inconsistent
transaction size attributes for locked
operation
N53 X X X X X Fixed
Multiple accesses to the same S-state
L2 cache line and ECC error
combination may result in loss of cache
coherency
N54 X X X X Fixed
Processor may hang when resuming
from Deep Sleep state
N55 X X X X X X X X No Fix
When the processor is in the System
Management Mode (SMM), debug
registers may be fully writeable
To Next Page
Loading...
Need help?
General
