Summary Tables of Changes
Specification Update 17
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N56 X X X X Fixed
Associated counting logic must be
configured when using Event Selection
Control (ESCR) MSR
N57 X X X X X X X X No Fix
IA32_MC0_ADDR and IA32_MC0_MISC
registers will contain invalid or stale
data following a Data, Address, or
Response Parity Error
N58 X X X X X Fixed
CR2 may be incorrect or an incorrect
page fault error code may be pushed
onto stack after execution of an LSS
instruction
N59 X Fixed
BPM[5:3]# V
IL
does not meet
specification
N60 X X X X No Fix
Processor may hang under certain
frequencies and 12.5% STPCLK# duty
cycle
N61 X X X X X X X X No Fix
System may hang if a fatal cache error
causes Bus Write Line (BWL)
transaction to occur to the same cache
line address as an outstanding Bus
Read Line (BRL) or Bus Read-Invalidate
Line (BRIL)
N62 X X X X X Fixed
L2 cache may contain stale data in the
Exclusive state
N63 X X X X X X Fixed
Re-mapping the APIC base address to
a value less than or equal to
0xDC001000 may cause IO and Special
Cycle failure
N64 X X X Fixed
Erroneous BIST result found in EAX
register after reset
N65 X X X X X Fixed
Processor does not flag #GP on non-
zero write to certain MSRs
N66 X X X X X X X X No Fix
Simultaneous assertion of A20M# and
INIT# may result in incorrect data
fetch
N67 X X X X X Fixed
CPUID instruction returns incorrect
number of ITLB entries
N68 X X X X X X X X No Fix
A Write to an APIC Register Sometimes May
Appear to Have Not Occurred
N69 X X
Plan
Fix
STPCLK# Signal Assertion under
Certain Conditions May Cause a
System Hang
N70 X Fixed
Store to Load Data Forwarding may
Result in Switched Data Bytes
N71 X X X X No Fix
Parity Error in the L1 Cache may Cause
the Processor to Hang
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