Summary Tables of Changes
18 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N72 X X Fixed
The TCK Input in the Test Access Port
(TAP) is Sensitive to Low Clock Edge
Rates and Prone to Noise Coupling
Onto TCK's Rising or Falling Edges
N73 X X X No Fix
Disabling a Local APIC Disables Both
Logical Processor APICs on a Hyper-
Threading Technology Enabled
Processor
N74 X X
Plan
Fix
A circuit marginality in the 800 MHz
Front Side Bus power save circuitry
may cause a system and/or application
hang or may result in incorrect data
N75 X X X No Fix
Using STPCLK# and Executing Code
From Very Slow Memory Could Lead to
a System Hang
N76 X X X X X X No Fix
Changes to CR3 Register do not Fence
Pending Instruction Page Walks
N77 X X X X X X X X No Fix
The State of the Resume Flag (RF Flag)
in a Task-State Segment (TSS) May be
Incorrect
N78 X X X X X X X X No Fix
Processor Provides a 4-Byte Store
Unlock After an 8-Byte Load Lock
N79 X X
1
X
1
Plan
Fix
Simultaneous Page Faults at Similar
Page Offsets on Both Logical Processors
of an Hyper-Threading Technology
Enabled Processor May Cause
Application Failure
N80 X X X X X X X X No Fix
System Bus Interrupt Messages
Without Data Which Receive a
HardFailure Response May Hang the
Processor
N81 X X X X X X X X No Fix
Memory Type of the Load Lock
Different from its Corresponding Store
Unlock
N82 X X X No Fix
Shutdown and IERR# May Result Due
to a Machine Check Exception on a
Hyper-Threading Technology Enabled
Processor
N83 X X X X X X X X
Plan
Fix
A 16-bit Address Wrap Resulting from
a Near Branch (Jump or Call) May
Cause an Incorrect Address to Be
Reported to the #GP Exception Handler
N84 X
Plan
Fix
Simultaneous Cache Line Eviction From
L2 and L3 Caches may Result in the
Write Back of Stale Data
N85 X X X No Fix
Locks and SMC Detection May Cause
the Processor to Temporarily Hang
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