Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor - Alphabetical Land Assignments

Land Listing and Signal Descriptions
Datasheet 47
D32# G16 Source Synch Input/Output
D33# E15 Source Synch Input/Output
D34# E16 Source Synch Input/Output
D35# G18 Source Synch Input/Output
D36# G17 Source Synch Input/Output
D37# F17 Source Synch Input/Output
D38# F18 Source Synch Input/Output
D39# E18 Source Synch Input/Output
D40# E19 Source Synch Input/Output
D41# F20 Source Synch Input/Output
D42# E21 Source Synch Input/Output
D43# F21 Source Synch Input/Output
D44# G21 Source Synch Input/Output
D45# E22 Source Synch Input/Output
D46# D22 Source Synch Input/Output
D47# G22 Source Synch Input/Output
D48# D20 Source Synch Input/Output
D49# D17 Source Synch Input/Output
D50# A14 Source Synch Input/Output
D51# C15 Source Synch Input/Output
D52# C14 Source Synch Input/Output
D53# B15 Source Synch Input/Output
D54# C18 Source Synch Input/Output
D55# B16 Source Synch Input/Output
D56# A17 Source Synch Input/Output
D57# B18 Source Synch Input/Output
D58# C21 Source Synch Input/Output
D59# B21 Source Synch Input/Output
D60# B19 Source Synch Input/Output
D61# A19 Source Synch Input/Output
D62# A22 Source Synch Input/Output
D63# B22 Source Synch Input/Output
DBI0# A8 Source Synch Input/Output
DBI1# G11 Source Synch Input/Output
DBI2# D19 Source Synch Input/Output
DBI3# C20 Source Synch Input/Output
DBR# AC2 Power/Other Output
DBSY# B2 Common Clock Input/Output
DEFER# G7 Common Clock Input
DPRSTP# T2 Asynch CMOS Input
DPSLP# P1 Asynch CMOS Input
DRDY# C1 Common Clock Input/Output
DSTBN0# C8 Source Synch Input/Output
DSTBN1# G12 Source Synch Input/Output
DSTBN2# G20 Source Synch Input/Output
DSTBN3# A16 Source Synch Input/Output
Table 4-1. Alphabetical Land
Assignments
Land Name Land #
Signal Buffer
Type
Direction
DSTBP0# B9 Source Synch Input/Output
DSTBP1# E12 Source Synch Input/Output
DSTBP2# G19 Source Synch Input/Output
DSTBP3# C17 Source Synch Input/Output
FC0/
BOOTSELECT
Y1 Power/Other
FC3 J2 Power/Other
FC8 AK6 Power/Other
FC10 E24 Power/Other
FC15 H29 Power/Other
FC18 AE3 Power/Other
FC20 E5 Power/Other
FC21 F6 Power/Other
FC22 J3 Power/Other
FC23 A24 Power/Other
FC24 AK1 Power/Other
FC25 AL1 Power/Other
FC26 E29 Power/Other
FC29 U2 Power/Other
FC30 U3 Power/Other
FC31 J16 Power/Other
FC32 H15 Power/Other
FC33 H16 Power/Other
FC34 J17 Power/Other
FC35 H4 Power/Other
FC36 AD3 Power/Other
FC37 AB3 Power/Other
FC39 AA2 Power/Other
FC40 AM6 Power/Other
FERR#/PBE# R3 Asynch CMOS Output
GTLREF0 H1 Power/Other Input
GTLREF1 H2 Power/Other Input
GTLREF2 F2 Power/Other Input
GTLREF3 G10 Power/Other Input
HIT# D4 Common Clock Input/Output
HITM# E4 Common Clock Input/Output
IERR# AB2 Asynch CMOS Output
IGNNE# N2 Asynch CMOS Input
INIT# P3 Asynch CMOS Input
ITP_CLK0 AK3 TAP Input
ITP_CLK1 AJ3 TAP Input
LINT0 K1 Asynch CMOS Input
LINT1 L1 Asynch CMOS Input
LOCK# C3 Common Clock Input/Output
MSID0 W1 Power/Other Output
MSID1 V1 Power/Other Output
Table 4-1. Alphabetical Land
Assignments
Land Name Land #
Signal Buffer
Type
Direction