Intel Q9300 - Core 2 Quad 2.5 GHz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor - Numerical Land Assignment

Land Listing and Signal Descriptions
Datasheet 59
B12 D13# Source Synch Input/Output
B13 COMP8 Power/Other Input
B14 VSS Power/Other
B15 D53# Source Synch Input/Output
B16 D55# Source Synch Input/Output
B17 VSS Power/Other
B18 D57# Source Synch Input/Output
B19 D60# Source Synch Input/Output
B2 DBSY# Common Clock Input/Output
B3 RS0# Common Clock Input
B4 D00# Source Synch Input/Output
B5 VSS Power/Other
B6 D05# Source Synch Input/Output
B7 D06# Source Synch Input/Output
B8 VSS Power/Other
B9 DSTBP0# Source Synch Input/Output
B20 VSS Power/Other
B21 D59# Source Synch Input/Output
B22 D63# Source Synch Input/Output
B23 VSSA Power/Other
B24 VSS Power/Other
B25 VTT Power/Other
B26 VTT Power/Other
B27 VTT Power/Other
B28 VTT Power/Other
B29 VTT Power/Other
B30 VTT Power/Other
C1 DRDY# Common Clock Input/Output
C2 BNR# Common Clock Input/Output
C3 LOCK# Common Clock Input/Output
C4 VSS Power/Other
C5 D01# Source Synch Input/Output
C6 D03# Source Synch Input/Output
C7 VSS Power/Other
C8 DSTBN0# Source Synch Input/Output
C9 BPMb1# Common Clock Input/Output
C10 VSS Power/Other
C11 D11# Source Synch Input/Output
C12 D14# Source Synch Input/Output
C13 VSS Power/Other
C14 D52# Source Synch Input/Output
C15 D51# Source Synch Input/Output
C16 VSS Power/Other
C17 DSTBP3# Source Synch Input/Output
C18 D54# Source Synch Input/Output
C19 VSS Power/Other
Table 4-2. Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
C20 DBI3# Source Synch Input/Output
C21 D58# Source Synch Input/Output
C22 VSS Power/Other
C23 VCCIOPLL Power/Other
C24 VSS Power/Other
C25 VTT Power/Other
C26 VTT Power/Other
C27 VTT Power/Other
C28 VTT Power/Other
C29 VTT Power/Other
C30 VTT Power/Other
D1 RESERVED
D2 ADS# Common Clock Input/Output
D3 VSS Power/Other
D4 HIT# Common Clock Input/Output
D5 VSS Power/Other
D6 VSS Power/Other
D7 D20# Source Synch Input/Output
D8 D12# Source Synch Input/Output
D9 VSS Power/Other
D10 D22# Source Synch Input/Output
D11 D15# Source Synch Input/Output
D12 VSS Power/Other
D13 D25# Source Synch Input/Output
D14 RESERVED
D15 VSS Power/Other
D16 RESERVED
D17 D49# Source Synch Input/Output
D18 VSS Power/Other
D19 DBI2# Source Synch Input/Output
D20 D48# Source Synch Input/Output
D21 VSS Power/Other
D22 D46# Source Synch Input/Output
D23 VCCPLL Power/Other
D24 VSS Power/Other
D25 VTT Power/Other
D26 VTT Power/Other
D27 VTT Power/Other
D28 VTT Power/Other
D29 VTT Power/Other
D30 VTT Power/Other
E2 VSS Power/Other
E3 TRDY# Common Clock Input
E4 HITM# Common Clock Input/Output
E5 FC20 Power/Other
E6 RESERVED
Table 4-2. Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction