Name: Intel Xeon Phi
Brand: Intel
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Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE

Code Example 11: Prefixing an Intel TBB Class for Intel® MIC Architecture code generation in C/C++

2. Prefix the function to be offloaded to the Intel® Xeon Phi™ Coprocessor by

__attribute__((target(mic)))

float MICReductionTBB(float *data, int size)

{

ReduceTBB redc(data);

// initializing the library

task_scheduler_init init;

parallel_reduce(blocked_range<size_t>(0, size), redc);

return redc.sum;

}

Code Example 12: Prefixing an Intel TBB Function for Intel® MIC Architecture code generation in C/C++

3. Use #pragma offload target(mic) to offload the parallel code using Intel TBB to the coprocessor

float MICReductionTBB(float *data, int size)

{

float ret(0.f);

#pragma offload target(mic) in(size) in(data:length(size)) out(ret)

ret = _MICReductionTBB(data, size);

return ret;

}

Code Example 13: Offloading Intel TBB Code to the coprocessor in C/C++

NOTE: Codes using Intel TBB with an offload should be compiled with –tbb flag instead of –ltbb.

Using Intel

MKL

For offload users, Intel MKL is most commonly used in Native Acceleration (NAcc) mode on the Intel® Xeon Phi™

Coprocessor. In NAcc, all data and binaries reside on the Intel® Xeon Phi™ Coprocessor. Data is transferred by

the programmer through offload compiler pragmas and semantics to be used by Intel MKL calls within an

offloaded region or function. NAcc functionality contains BLAS, LAPACK, FFT, VML, VSL, (Sparse Matrix Vector),

and required Intel MKL Service functions. Please see the Intel MKL release documents for details on which

functions are optimized and which are not supported.

The Native Acceleration Mode can also be used in native Intel® MIC Architecture code – in this case the Intel

MKL shared libraries must be copied to the Intel® Xeon Phi™ Coprocessor before execution.

Intel Xeon Phi User Manual

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