Intel® Xeon Phi™ Coprocessor DEVELOPER’S QUICK START GUIDE
4
Introduction
This document will help you get started writing code and running applications on a system (host) that includes
the Intel® Xeon Phi™ Coprocessor based on the Intel® Many Integrated Core Architecture (Intel® MIC
Architecture). It describes the available tools and includes simple examples to show how to get C/C++ and
Fortran-based programs up and running. For now, the developer will have to cut/paste the examples provided
in the document to their system.
This document is available at http://software.intel.com/mic-developer under the “Overview” tab.
Goals
This document does:
1. Walk you through the Intel® Manycore Platform Software Stack (Intel® MPSS) installation.
2. Introduce the build environment for software enabled to run on Intel® Xeon Phi™ Coprocessor.
3. Give an example of how to write code for Intel® Xeon Phi™ Coprocessor and build using Intel®
Composer XE 2013 SP1.
4. Demonstrate the use of Intel libraries like the Intel® Math Kernel Library (Intel® MKL).
5. Point you to information on how to debug and profile programs running on an Intel® Xeon Phi™
Coprocessor.
6. Share some best known methods (BKMs) developed by users at Intel.
This document does not:
1. Cover each tool in detail. Please refer to the user guides for the individual tools.
2. Provide in-depth training.
Terminology
Host – The Intel® Xeon® platform containing the Intel® Xeon Phi™ Coprocessor installed in a PCIe* slot. The
operating systems (OS) supported on the host are Red Hat* Enterprise Linux* 6.0, Red Hat* Enterprise Linux*
6.1, Red Hat* Enterprise Linux* 6.2, Red Hat* Enterprise Linux* 6.3, Red Hat* Enterprise Linux* 6.4, Red Hat*
Enterprise Linux* 6.5, SUSE* Linux* Enterprise Server SLES 11 SP2 and SUSE* Linux* Enterprise Server SLES
11 SP3. The user will have to install the OS.
Target – The Intel® Xeon Phi™ Coprocessor and corresponding runtime environment installed inside the
coprocessor.
uOS – Micro Operating System – the Linux
*
-based operating system and tools running on the Intel® Xeon Phi™
Coprocessor.
ISA – Instruction Set Architecture – part of the computer architecture related to programming, including the
native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception
handling, and external I/O (Input/Output).
VPU – Vector Processing Unit- the portion of a CPU responsible for the execution of SIMD (single instruction,
multiple data) instructions.
Intel acronyms dictionary, 8/6/2009, http://library.intel.com/Dictionary/Details.aspx?id=5600
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