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LG Flatron W1941S - Block Diagram Explanations

LG Flatron W1941S
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DESCRIPTION OF BLOCK DIAGRAM
1. Video Controller Part.
This part amplifies the level of video signal for the digital conversion and converts from the analog video signal to
the digital video signal using a pixel clock.
The pixel clock for each mode is generated by the PLL.
The range of the pixel clock is from 79.5MHz to 90MHz.
This part consists of the Scaler, ADC converter, TMDS receiver and LVDS transmitter.
The Scaler gets the video signal converted analog to digital, interpolates input to 1360 X 768 resolution signal and
outputs 8-bit R, G, B signal to transmitter.
2. Power Part.
This part consists of the one 3.3V, and one 1.8V regulators to convert power which is provided 5V in Power board.
12V is provided for inverter, 5V is provided for LCD panel.
Also, 5V is converted 3.3V and 1.8V by regulator. Converted power is provided for IC in the main board.
The inverter converts from DC 12V to AC 700Vrms and operates back-light lamps of module.
3. MICOM Part.
This part is including video controller part. And this part consists of NVRAM which stores control data, Reset IC and
the Micom.
The Micom distinguishes polarity and frequencies of the H/V sync are supplied from signal cable.
The controlled data of each mode is stored in NVRAM.
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