LG Flatron W2442PA - SYSTEM BLOCK DIAGRAM

Copyright
L V D S
L V D SL V D S
Analog I(R/G/B)
D-Sub
LIPS
Filter
5V
22V
5V
Regulator
Regulator
3.3V
Vcc 5V
3.3V
Inverter(4Lamps)
22V
22V
DVI-D
DVI(TMDS)
KEY
1.8V
1.8V
Module
SDA /SCL
EEPROM
(EDID)
EEPROM
(EDID)
EEPROM
(System)
EEPROM
(System)
3.3V
EEPROM
(EDID)
EEPROM
(EDID)
1920X1080@60Hz
148.5Mhz
Dual
Interface
Engine
Display
Processing
Engine
Response
Time
Enhanceme nt
LVDS
Panel
Interface
OSD
Clock
Generator
MCU
DRAM
TSUMU88EDI-5
Flash ROM
Flash ROM
3.3V
Crystal
Crystal
14.318MHz
HDMI
HDMI(TMDS)
EEPROM
(EDID)
EEPROM
(EDID)
BLOCK DIAGRAM
- 10 -
2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only