LG HDR676X - Timer Block Diagram

14. TIMER BLOCK DIAGRAM
5.3VA(SW), FD+(SW)STANBY_H
I/O U-COM PWR CTL
F
D +(SW)
FLD( + )
FLD( + )
FD( - )
FLD( - )
FLD( - )
29VA
FLD Driv e IC
(PT6315)
FLD Driv e IC
(PT6315)
5.3VA
Remoc on Reciver
Remoc on Reciver
5.3VA(SW)
3-41 3-42