Symbol Ty pe Description
CLK Input
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE Input
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When both
banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device
enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK, are
disabled during Power Down and Self Refresh modes, providing low standby
power.
A11 Input
Bank Select:
A11(BS) defines to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
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