Linear Technology LTC6804-1 - Page 69

LTC6804-1/LTC6804-2
69
680412fc
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applicaTions inForMaTion
Implementing a Modular isoSPI Daisy Chain
The hardware design of a daisy-chain isoSPI bus is identi-
cal for each device in the network due to the daisy-chain
point-to-point
ar
chitecture. The simple design as shown in
Figure 41 is functional, but inadequate for most designs. The
termination resistor R
M
should be split and bypassed with
a capacitor as shown in Figure 43. This change provides
both a differential and a common mode termination, and
as such, increases the system noise immunity.
The use of cables between battery modules, particularly
in automotive applications, can lead to increased noise
susceptibility in the communication lines. For high levels
of electromagnetic interference (EMC), additional filtering
is recommended. The circuit example in Figure 43 shows
the use of common mode chokes (CMC)to add common
mode noise rejection from transients on the battery lines.
The use of a center tapped transformer will also provide
additional noise performance. A bypass capacitor con
-
nected to the center tap creates a low impedance for
common mode noise (Fi
gure 43b). Since transformers
without a center tap can be less expensive, they may be
preferred. In this case, the addition of a split termination
resistor and a bypass capacitor (Figure 43a) can enhance
the isoSPI performance. Large center tap capacitors
greater than 10nF should be avoided as they may prevent
the isoSPI common mode voltage from settling. Common
mode chokes similar to those used in Ethernet or CANbus
applications are recommended. Specific examples are
provided in Table49.
isoSPI LINK
XFMR
isoSPI LINK
CT XFMR
LTC6804-1
LTC6804-1
IP
IM
V
–
10nF
100µH CMC
10nF
••
62Ω
62Ω
300Ω
300Ω
••
a)
IP
IM
V
–
10nF
100µH CMC
10nF
••
51Ω
51Ω
••
b)
680412 F43
Figure 43. Daisy Chain Interface Components
An important daisy chain design consideration is the
number of devices in the isoSPI network. The length of the
chain determines the serial timing and affects data latency
and throughput. The maximum number of devices in an
isoSPI daisy chain is strictly dictated by the serial timing
requirements. However, it is important to note that the serial
read back time, and the increased current consumption,
might dictate a practical limitation.
For a daisy chain, two timing considerations for proper
operation dominate (see Figure 20):
1. t
6
, the time between the last clock and the rising chip
select, must be long enough.
2. t
5
, the time from a rising chip select to the next falling
chip select (between commands), must be long enough.
Both t
5
and t
6
must be lengthened as the number of
LTC6804 devices in the daisy chain increases. The equa-
tions for these times are below:
t
5
> (#devices • 70ns) + 900ns
t
6
> (#devices • 70ns) + 950ns