37
Q201 : NJU3713A
Package Outline
SSOP20
P5
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
P4
P3
P2
P1
NC
CLR
STB
CLK
DATA
P6
P7
P8
V
NC
P9
P10
P11
P12
PIN CONFIGURATION
P1
Shift Register
Latch Circuit
P2
P3
P11
P12
DAT
CL
STB
CLR
BLOCK DIAGRAM
No. SYMBOL I/O FUNCTION
1 P5 O
2 P6 O
3 P7 O
4 P8 O
Parallel Conversion Data Output Terminals
5 V
SS
- GND
6 NC - Non Connection
7 P9 O
8 P10 O
9 P11 O
10 P12 O
Parallel Conversion Data Output Terminals
11 DATA I Serial Data Input Terminal
12 CLK I Clock Signal Input Terminal
13
STB
I Strobe Signal Input Terminal
14
CLR
I Clear Signal Input Terminal
15 NC - Non Connection
16 P1 O
17 P2 O
18 P3 O
19 P4 O
Parallel Conversion Data Output Terminals
20 V
DD
- Power Supply Terminal (2.4 to 5.5V)
TERMINAL DESCRIPTION