Marantz SR-19EX - Page 30

53 54
18
AIN1
6
REFERENCE
DIVIDER
PHASE DETECTOR
CHARGE PUMP
SWALLOW COUNTER
1/16, 1/17 4blt
1
24
15
14
3
4
5
16
X IN
XOUT
FM IN
1
2
AM IN
CE
DI
CL
DO
12blt PROGRAMMABLE
DIVIDER
DATA SHIFT REGISTER
LATCH
7
89
10
211
13
BO1
BO2 BO3 BO4 BO5
IO1
IO2
UNIVERSAL
COUNTER
12
17
20
19
23
V
SS
AOUT1
PD2
PD1
LC72130
IFIN
21
AIN2
22
AOUT2
UNLOCK
DETECTOR
CCB
I/F
V DD
POWER
ON
RESET
Q501:LC72130
QR01:LC89055Q
Microcontroller interface
C data
detection
DI
CE
DO
Data
demodulation
block
Input
block
Lock error
detection
PLL Timing
DATAO
ERROR
VIN
DIN2
R
DIN0
DIN1
LPF
Pa, Pb
detection
fs calculation
37
36
24
3
4
5
8
9
10
AUDIO
35
34
16
CKOUT
BCK
LRCK
13
14
15
F0/P0/C0
F1/P1/C1
F2/P2/C2
27
28
29
CL
38
AUTO
26
CSFLAG
25
DOUT
DISEL
1
2
23
EMPHA
MODE0
40
MODE1
41
DOSEL0
44
X'tal1XOUT
XIN
XMCK
22
21
20
CKSEL0
46
XSEL
39
VF/P3/C3
32
XMODE
48
XSTATE
17
CKSEL1
47
DOSEL1
45
BPSYNC
33
I
I/O
I/O
I/O
I/O
I/O
pin port name I/O use Name Act. Note
41
P10/AD8 I/O O _RSTRF L Reset RF demodulate
42
P11/AD9 I/O O D_A - Digital / _Analog select
43
P12/AD10 I/O O DEMP H Emphasis to S-Direct
44
P13/AD11 I/O O _UMUTE L Hard Mute for Tr
45
P14/AD12 I/O O FS96 H 96kHz fs
46
P15/AD13 I/O O BYPASS 1 H Bypass DSP1
47
P16/AD14 I/O O _BYPASS 2 L Bypass DSP2
48
P17/AD15
I/O
I/O
I/O
I/O
I/O
O _CS_DSP1 L _CS_DSP1(main DSP)
49
P20/A0 O _CSB_DSP1 L _CS DSP1(sub DSP)
50
P21/A1 I/O O _SS_DSP2 L _SS DSP2(Zoran)
51
P22/A2 O _CE_DIR L _CE for DIR
52
P23/A3 I/O O _RSTDSP2 L Reset DSP2
53
P24/A4 O _RSTDA1 L Reset DAC for L/R
54
P25/A5 I/O O _RSTDA2 L Reset DAC except L/R
55
P26/A6 O _IC L Reset DSP1
56
P27/A7 I/O O _XMODE L _Reset DIR
57
Vcc Vcc +5VD
- Vcc
58
P30/RD O O _RSTAD L Reset & Cal for ADC
59
P31/WR O O _IFACK L Ack to main CPU
60
P32/SCK I/O I IFSCK - Clock from main CPU
61
P33/SO I/O O IFDO - Data to main CPU
62
P34/SI I/O I IFDI - Data from main CPU
63
P35/INT0 INT OVFB H Over Level (sub DSP)
64
P40/INT1 I/O INT XSTATE H MCLK status(L:/unstable)
65
P41/TO3 I CAL H ADC Calibration
66
P42/INT4 I/O INT _RFNODET L _No RF signal
67
P43/INT5 INT ERF H DIR Error
68
P44/TO4 I/O O - - -
69
P45/INT6 INT _IFREQ L Request from main CPU
70
P46/INT7 I/O I CSFLAG H Ch. Status(fall edge DIR)
71
P47/TO6 O - - -
72
VrefH I VrefH +5VD - ref High voltage for int. AD
73
VrefL VrefL GND
- ref Low voltage for int. AD
74
Avss I Avss GND - GND for Int. AD
75
Avcc Avcc +5VD
- Vcc for Int. AD
76
P50/AN0 I AN KEY_INPUT0 - Optional 8 key input 0
77
P51/AN1
I
I
I AN KEY_INPUT1 - Optional 8 key input 1
78
P52/AN2 I AN KEY_INPUT2 - Optional 8 key input 2
79
P53/AN3 I AN KEY_INPUT3 - Optional 8 key input 3
80
P54/AN4 I AN KEY_INPUT4 - Optional 8 key input 4
I
I
I
pin port name I/O use Name Act. Note
1
P55/AN5 MODE_SW0 -
Link Host or _Stand alone
2
P56/AN6 I MODE_SW1 - _HDCD available
3
P57/AN7 MODE_SW2 - _RF available
4
NMI I - - - to GND
5
P60/TXD0 I/O O DO0 Data out to DSP1&2
6
P61/RXD0 I/O I DI0 Data In from DSP1&2
7
P62/SCLK0 I/O O SCLK0 Clock Out to DSP1&2
8
P63/TXD1 I/O O DO1 Data out to DIR
9
P64/RXD1 I/O I DI1 Data In from DIR
10
P65/SCLK1 I/O O SCLK1 Clock Out to DIR
11
P70/WAIT I/O O T0 L to check LED
12
P71 I/O O T1 L to check LED
13
Vss Vss GND
- GND
14
P72 I/O O T2 L to check LED
15
P73 I/O O T3 L to check LED
16
P74 I/O O T4 L to check LED
17
P75 /O O X2GAIN L HDCD PE
18
P76 I/O I HDCD H detect HDCD
19
P77
I/
I/O O K_TEST L to check LED
20
CLK O - n.c. - pull µP
21
AM8/16 - n.c.
- pull µP
22
X1
I
I
X1 20MHz -
Q691:TMP93CW44ADF