Marvell 88E1111 - Page 18

Doc. No. MV-S105540-00, Rev. A
Page 18 Document Classification: Proprietary Information
The RGMII interface supports 10/100/1000BASE-T and 1000BASE-X modes of operation.The RGMII interface
pins are also used for the RTBI interface. See Ta b le 5 for RTBI pin definitions. The MAC interface pins are 3.3V
tolerant.
Table 4: RGMII Interface
117-TFBGA
Pin #
96-aQFN
Pin #
128-PQFP
Pin #
Pin Name Pin
Type
Description
E2 B4 14 GTX_CLK/
TXC
I RGMII Transmit Clock provides a 125 MHz,
25 MHz, or 2.5 MHz reference clock with ±
50 ppm tolerance depending on speed. In
RGMII mode, GTX_CLK is used as TXC.
H2
G3
G2
F1
B8
B7
B6
A6
24
20
19
18
TXD[3]/TD[3]
TXD[2]/TD[2]
TXD[1]/TD[1]
TXD[0]/TD[0]
I RGMII Transmit Data. In RGMII mode,
TXD[3:0] are used as TD[3:0].
In RGMII mode, TXD[3:0] run at double data
rate with bits [3:0] presented on the rising
edge of GTX_CLK, and bits [7:4] presented
on the falling edge of GTX_CLK. In this
mode, TXD[7:4] are ignored.
In RGMII 10/100BASE-T modes, the trans-
mit data nibble is presented on TXD[3:0] on
the rising edge of GTX_CLK.
E1 A5 16 TX_EN/
TX_CTL
I RGMII Transmit Control. In RGMII mode,
TX_EN is used as TX_CTL. TX_EN is pre-
sented on the rising edge of GTX_CLK.
A logical derivative of TX_EN and TX_ER is
presented on the falling edge of GTX_CLK.
C1 B1 7 RX_CLK/
RXC
O, Z RGMII Receive Clock provides a 125 MHz,
25 MHz, or 2.5 MHz reference clock with ±
50 ppm tolerance derived from the received
data stream depending on speed. In RGMII
mode, RX_CLK is used as RXC.
88E1111 Product Brief
Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver
Copyright © 2020 Marvell
December 2, 2020