Maxim Integrated Page 18 of 52
I
2
C Read
The process for an I
2
C read data transfer is as follows:
1. The bus master indicates a data transfer to the device with a START condition.
2. The master transmits one byte with the 7-bit slave address and a single write bit set to zero. The
eight bits to be transferred as a slave address for the MAX32664 is 0xAA for a write transaction.
This write transaction precedes the actual read transaction to indicate to the device what section
is to be read.
3. During the next SCL clock following the write bit, the master releases SDA. During this clock period,
the device responds with an ACK by pulling SDA low.
4. The master senses the ACK condition and begins to transfer the Family Byte. The master drives
data on the SDA circuit for each of the eight bits of the Family byte, and then floats SDA during
the ninth bit to allow the device to reply with the ACK indication.
5. The master senses the ACK condition and begins to transfer the Index Byte. The master drives
data on the SDA circuit for each of the eight bits of the Index byte, and then floats SDA during the
ninth bit to allow the device to reply with the ACK indication.
6. The master senses the ACK condition and begins to transfer the Write Data Byte if necessary for
the read instruction. The master drives data on the SDA circuit for each of the eight bits of the
Write Data byte, and then floats SDA during the ninth bit to allow the device to reply with the ACK
indication.
7. The master indicates the transfer is complete by generating a STOP condition.
8. The master waits for a period of CMD_DELAY (2 msec60µs) for the device to have its data ready.
9. The master indicates a data transfer to a slave with a START condition.
10. The master transmits one byte with the 7-bit slave address and a single write bit set to one. This
is an indication from the master of its intent to read the device from the previously written
location defined by the Family Byte and the Index Byte. The master then floats SDA and allows
the device to drive SDA to send the Status Byte. The Status Byte reveals the success of the previous
write sequence. After the Status Byte is read, the master drives SDA low to acknowledge the byte.
11. The master floats SDA and allows the device to drive SDA to send Read Data Byte 0. After Read
Data Byte 0 is read, the master drives SDA low to acknowledge the byte.
12. The master floats SDA and allows the device to drive SDA to send the Read Data Byte N. After
Read Data Byte N is read, the master drives SDA low to acknowledge the Read Data Byte N. This
process continues until the device has provided all the data that the master expects based upon
the Family Byte and Index Byte definition.
13. The master indicates the transfer is complete by generating a STOP condition.
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