7I90HD 12
OPERATION
EPP HOST INTERFACE
The EPP host interface option allows the 7I90HD to connect to EPP compatible
parallel port on PCs for a medium speed real time interface. The interface from host EPP
printer port to the FPGA uses 12 FPGA pins. These consist of an eight bit bidirectional
data bus (D0..D7), and four handshake lines.
P4 PIN EPPNAME SPPNAME FPGA PIN DIRECTION
1 /WRITE /STROBE 40 TO FPGA
2 /DSTROBE /AUTOFD 41 TO FPGA
8 /ASTROBE /SELECTIN 48 TO FPGA
21 WAIT BUSY 61 FROM FPGA
3 D0 D0 43 BIDIR
5 D1 D1 45 BIDIR
7 D2 D2 47 BIDIR
9 D3 D3 51 BIDIR
11 D4 D4 55 BIDIR
13 D5 D5 56 BIDIR
15 D6 D6 57 BIDIR
17 D7 D7 58 BIDIR
With standard HostMot2 EPP configurations, minumum AStrobe and Dstrobe
durations are 200 nS. Read data is available in less than 70 nS from the strobe. Write data
is sampled by the 7I90 180 nS from the beginning of the strobe, and wait is deasserted
200 nS from the beginning of the strobe.
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