7I90HD 13
OPERATION
SPI HOST INTERFACE
GENERAL
The SPI host interface is a medium speed real time host interface with a low pin
count for microcontrollers and SOC’s that have built in SPI interface hardware. The
7I90HDs SPI interface is a slave interface and uses a SPI frame size of 32 bits for all
transactions. The interface supports a SPI clock rate up to 50 MHz.
SPI MODE
The host interface uses the convention that the clock idles low, host data is shifted
into the 7I90HD on the SPI clock rising edge, and data is shifted out of the 7I90HD on the
clock falling edge. This matches SPI master setup with CPOL=0 and CPHA=0. The CS pin
is active low. To support the highest transfer rates the master should have a "late sample"
option.
SPI HEADER
SPI transactions always starts with a 32 bit header which contains the target register
address, the read or write command, the number of data elements to be transferred and
the address increment bit.
SPI HEADER
A A A A A A A A A A A A A A A A C C C C I N N N N N N N X X X X
The first 16 bits ("A" in the table above) are the HostMot2 register address (byte
address), MSb first. The next 4 bits ("C") are the command. Currently only 2 commands
are supported, read (0xA) and write (0xB). The next bit ("I") is the address increment bit.
When this bit is set, the register address is incremented (by 4) after every register
read/write access, allowing burst transfers from groups of sequential registers without
requiring a new address to be sent. Burst transfers with the increment bit cleared can be
used for multiple reads/writes to a single address for FIFO access and similar applications.
The next 7 bits ("N") are the burst length for sequential transfers.Valid burst lengths are 1
through 127. The "X" bits are unused.
TRANSFER SEQUENCE
For SPI reads the master sends the header followed by N frames of 32 dummy (0)
bits, N being the burst length specified in the SPI header. The read data is returned on
each 32 bit frame after the header frame.
On writes, the N frames of write data are sent by the master following the SPI
header. The 7I90HD returns dummy data when write data is being received.
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