Mitsubishi Electric MELSEC iQ-R Series - Argument Specification

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1 COMMON ITEMS
1.3 MELSEC iQ-R Series Data Link Functions
Argument specification
This section shows the argument specification of the MELSEC iQ-R series data link functions.
Channel
A channel implies a network and communication route to be used when communicating with a C intelligent function module.
A channel number is set for each module in a user program.
A channel to be used for MELSEC iQ-R series data link functions is as follows:
CPU number, network number, start I/O number, station number
CPU numbers, Network numbers, start I/O numbers and station numbers to be specified to MELSEC iQ-R series data link
functions are as follows:
*1 No error will occur even if the value is set.
*2 A specified control station of the network, which is specified to the network number, is accessed. To access a station that is actually
operating as the control station, specify the station number.
Device type
The following table shows the device types specified to the MELSEC iQ-R series data link functions.
Devices are defined in the header file (MDRFunc.h).
Either a code or a device name can be specified as a device type.
Channel
number
Network Communication route
12 Bus interface Used for communication via bus.
Access route CPU number Network
number
Start I/O number Station number
Bus interface Own station • 0:
Control CPU
specification
• 1 to 4:
Multiple CPU
specification

*1

*1

*1
CC-Link IE Controller Network Via single network 1 to 239 1 to 120,
0
*2
, 125
*2
CC-Link IE Field Network 0 to 120
MELSECNET/H network 1 to 64,
0
*2
, 125
*2
CC-Link 
*1
0000H to 00FEH 0 to 63
Device name (Device) Device type
Code Device name
Decimal Hexadecimal
Input relay (X) 11HDevX
Output relay (Y) 22HDevY
Latch relay (L) 33HDevL
Internal relay (M) 44HDevM
Special relay (SM) 55HDevSM
CPU buffer memory
*1,*2
CPU No.1 area (U3E0\G) 501 1F5H DevSPB1
CPU No.2 area (U3E1\G) 502 1F6H DevSPB2
CPU No.3 area (U3E2\G) 503 1F7H DevSPB3
CPU No.4 area (U3E3\G) 504 1F8H DevSPB4
Fixed cycle communication area
*1,*2
CPU No.1 area (U3E0\HG) 511 1FFH DevHSPB1
CPU No.2 area (U3E1\HG) 512 200H DevHSPB2
CPU No.3 area (U3E2\HG) 513 201H DevHSPB3
CPU No.4 area (U3E3\HG) 514 202H DevHSPB4
Annunciator (F) 66HDevF