Mitsubishi Electric Q13UDVCPU - Page 599

597
APPENDICES
A
Appendix 3 List of Special Register Areas
SD1903
CH2 external
I/O status
monitor
CH2 external
I/O status
monitor
• This register stores a value indicating the external I/O
signal status of CH2.
• Unused signal status is fixed at off.
• When Normal Mode is set for Operation Mode Setting
(high-speed counter function parameter), a value
according to the setting configured for Function Input
Logic Setting (high-speed counter function parameter) is
stored in the function input status. Therefore, when a
voltage is applied to the function input terminal while
Negative logic is set for Function input logic setting, this
register turns off.
• When other than A Phase/B Phase is selected for Count
Source Selection (high-speed counter function
parameter), the phase A input status and phase B input
status are fixed at off.
S (Every
END
processing)
New LCPU
SD1904
CH2
operation
mode
monitor
CH2
operation
mode
monitor
This register stores a value indicating the operation mode for
high-speed counter of CH2 set by the parameter.
• 0: Unused
• 1: Normal mode
• 2: Frequency measurement mode
• 3: Rotation speed measurement mode
• 4: Pulse measurement mode
• 5: PWM output mode
S (Every
END
processing)
New LCPU
SD1905
CH2 counter
type monitor
CH2 counter
type monitor
This register stores a value indicating the counter type for
high-speed counter of CH2 set by the parameter.
Counter selection is disabled (fixed at "0") when a value
stored to CH2 operation mode monitor (SD1904) is other
than "1" (normal mode).
• 0: Linear counter
• 1: Ring counter
S (Every
END
processing)
New LCPU
SD1906
CH2 selected
counter
function
CH2 selected
counter
function
This register stores a value indicating the selected counter
function for high-speed counter of CH2 set by the parameter.
Counter selection is disabled (fixed at "0") when a value
stored to CH2 operation mode monitor (SD1904) is other
than "1" (normal mode).
• 0: Count disabling function
• 1: Latch counter function
• 2: Sampling counter function
• 3: Count disabling/preset function
• 4: Latch counter/preset function
S (Every
END
processing)
New LCPU
SD1907
CH2 error
code
CH2 error
code
This register stores the error code of an error occurred in
CH2.
S (Every
END
processing)
New LCPU
SD1908
CH2 warning
code
CH2 warning
code
This register stores the warning code of a warning occurred
in CH2.
S (Every
END
processing)
New LCPU
Number Name Meaning Explanation
Set by
(When Set)
Corresponding
ACPUD9
Corresponding
CPU
b2 b1 b0b3b4b7 b5b15
0
0/1 0/1 0/1 0/1
0/1 0/1
b6
0/1
to
Phase Z input status
0: OFF
1: ON
Function input status
0: OFF
1: ON
Latch counter input status
0: OFF
1: ON
Phase A input status
0: OFF
1: ON
Phase B input status
0: OFF
1: ON
Coincidence output No.1
0: OFF
1: ON
Coincidence output No.2
0: OFF
1: ON
Fixed to 0.