Mitsubishi Electric R16MTCPU - Page 87

2 MOTION DEDICATED PLC INSTRUCTION
2.3 Precautions
85
2
Number of simultaneous issues for Multiple CPU dedicated instructions
When the number of blocks being used to communicate with each CPU in the Multiple CPU dedicated instruction
transmission area exceeds the set value for "maximum number of blocks used for the Multiple CPU dedicated instruction
setting" in the Multiple CPU setting (special registers SD796 to SD799 of PLC CPU), the system enters a state where the
Motion dedicated PLC instruction is not accepted (permissible number of executions exceeded state). At the time of Motion
dedicated instruction execution towards the target CPU, an abnormal complete status "0010H" is set in the complete status
device. If the complete device is omitted, no operation occurs at all.
An interlock can be created using special relays containing block-use information (SM796 to SM799 of the PLC CPU) so that
the permissible number of executions is not exceeded.
• Special relay of PLC CPU
• Special register of PLC CPU
*1 When setting a value outside the range, the register operates as the maximum value for the range of the Multiple CPU system
configuration.
When
Maximum number of blocks used for the Multiple CPU dedicated instruction setting (SD796 to 799)  Number
of empty blocks of the dedicated instruction transmission area < number of blocks used by the instruction
at the execution of a Motion dedicated PLC instruction, the instruction is not executed (it is a no operation
state) in the current scan, but executed in the next scan.
When inserting an interlock condition by "Block information using Multiple CPU dedicated instruction (SM796
to SM799)", set a value equal to or more than the number of blocks used by the instructions executed in
"Maximum number of blocks used for the Multiple CPU dedicated instruction setting (SD796 to SD799)"
Device No. Name Meaning Explanation Set by
SM796 Block information using Multiple CPU
dedicated instruction
(For CPU No.1)
OFF: Block is secured
ON: Block set by SD796
cannot be secured
Turns ON when the number of the
remaining blocks of the dedicated
instruction transmission area used for the
Multiple CPU dedicated instruction is less
than the number of blocks specified by
"SD796 to SD799".
Turns ON at instruction execution. Turns
OFF when empty area exists at END
processing.
System (When
instruction/END
processing
executed)
SM797 Block information using Multiple CPU
dedicated instruction
(For CPU No.2)
OFF: Block is secured
ON: Block set by SD797
cannot be secured
SM798 Block information using Multiple CPU
dedicated instruction
(For CPU No.3)
OFF: Block is secured
ON: Block set by SD798
cannot be secured
SM799 Block information using Multiple CPU
dedicated instruction
(For CPU No.4)
OFF: Block is secured
ON: Block set by SD799
cannot be secured
Device No. Name Meaning Explanation Set by
SD796 Maximum number of blocks used for the
Multiple CPU dedicated instruction setting
(For CPU No.1)
Maximum number of blocks
range for dedicated
instructions depends on the
number of CPUs in the
Multiple CPU system
configuration.
*1
2 CPU configuration: 2 to 599
3 CPU configuration: 2 to 299
4 CPU configuration: 2 to 199
(Default: 2)
Specifies the maximum number of blocks
used for the Multiple CPU dedicated
instruction.
When the dedicated instruction of
Multiple CPU is executed to the target
CPU, and the number of empty blocks of
the dedicated instruction transmission
area is less than the setting value of this
register, "SM796 to SM799" is turned ON,
which is used as the interlock signal for
consecutive execution of the dedicated
instruction of Multiple CPU.
User
(At 1 scan after
RUN)
SD797 Maximum number of blocks used for the
Multiple CPU dedicated instruction setting
(For CPU No.2)
SD798 Maximum number of blocks used for the
Multiple CPU dedicated instruction setting
(For CPU No.3)
SD799 Maximum number of blocks used for the
Multiple CPU dedicated instruction setting
(For CPU No.4)