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Setting options: [Auto], [5T] to [15T].
RAS# to CAS# delay (Trcd)
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance. Setting options: [Auto], [2T] to [7T].
Row Precharge Time (Trp)
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumulate its
charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to
retain data. This item applies only when synchronous DRAM is installed in the
system. Available settings: [Auto], [2T] to [7T].
Row to Row delay (Trrd)
When the Timing Mode is set to [Manual], the field is adjustable. Specifies the
active-to-active delay of different banks. Available settings: [Auto], [2T], [3T],
[4T].
1T/2T Memory Timing
This setting controls the SDRAM command rate. Selecting [1T] allows SDRAM
signal controller to run at 1T (T=clock cycles) rate. Selecting [2T] makes SDRAM
signal controller run at 2T rate. 1T is faster than 2T. Setting options: [1T], [2T].
LDT & PCI Bus Control
Press <Enter> and the following sub-menu appears:
Upstream / Downstream LDT Bus Width
These two item control the utilized widths of the HyperTransport link. Setting
options: [8 bit], [16 bit].
LDT Bus Frequency
This item specifies the maximum operating frequency of the link's transmitter
clock. Setting options: [Auto], [800 MHz], [600 MHz], [400 MHz], [200 MHz].
PCI1/PCI2 Master 0 WS Write
When [Enabled], writes to the PCI bus are executed with zero wait states. Setting
options: [Enabled], [Disabled].
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