Chapter 3
3-12
Advanced Chipset Features
DRAM CAS# Latency
The field controls the CAS latency, which determines the timing delay before
SDRAM starts a read command after receiving it. Setting options: By SPD,
2T and 3T. 2T increases system performance while 3T provides more stable
system performance. Setting to By SPD enables DRAM CAS# Latency auto-
matically to be determined by BIOS based on the configurations on the SPD
(Serial Presence Detect) EEPROM on the DRAM module.
Timing Setting Mode
The DRAM timing is controlled by the DRAM Timing Registers. The Timings
programmed into this register are dependent on the system design. Slower
rates may be required in certain system designs to support loose layouts or
slower memory. Setting options: Safe, Normal, Fast, Turbo, Ultra.
MA 1T/2T Select
This setting controls the SDRAM command rate. Selecting Normal allows
SDRAM signal controller to run at 1T (T=clock cycles) rate. Selecting Delay
1T makes SDRAM signal controller run at 2T rate. 1T is faster than 2T. Setting
options: Delay 1T, Normal.
Note: Change these settings only if you are familiar with the chipset.
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