- 9 -
RF PATTERN TESTING
NAD - C 546BEE PCB TESTING POINTS DIAGRAM
TESTING PROCEDURE
(1) Load the test disc (Sony Test CD YEDS-7) and set the unit into PLAY mode.
(2) Connect the scope to C3 (Pin 4 of IC701) and DGND (J215).
Scope setting: Coupling : AC.
Vertical sensitivity : 0.2 V/ div.
Horizontal time base : 0.5 µS/div.
(3) Observe the waveform is 1.5V p-p +/-5% and the eye pattern is at its best shape (see FIG. 1).
FIG. 1 (a) FIG. 1 (b) Poor eye pattern
FIG. 1 (C) Good eye pattern
1 3
4 6
SLT-
SLT+
FM-
FM+
DM-
DM+
FE-
TE-
TE+
FE+
PD
VR
LD
GND
F
C
B
A
D
E
SVCC
VREF
T5CJ3-7D13
TC94A93FG
CL-SW
OP/CL-COM
OP-SW
LM-CL
LL M-OP
GN D
USB-
USB-
USB-
DET
UPDATE
POWER
AM1
MCU-
TEST
USB-
RST
MCU-
RST
USB-
RX
USB-
TX
VCC
D-
D+
DGND
PCB-C546 26+SERVO
17 2 5-97 0B+000B
Q701
Q71
Q2
C707
C708
C712
C715
C717
C734
C735
C743
C744
C745
C746
C27
C28
C29
C52
C56
C6
C7
C701
C702
C705
C706
C710
C713
C714
C716
C719
C721
C723
C724
C728
C731
C733
C737
C738
C740
C742
C756
C760
C761
C765
C768
C770
C771
C772
C774
C775
C777
C781
C783
C757
C791
C711
C718
C726
C727
C763
C764
C703
C704
C720
C722
C725
C730
C732
C741
C766
C767
C769
C773
C776
C778
C779
C780
C782
C25
C51
C76
C60
C75
C739
C785
C26
C8
C758
C759
C762
C53
C54
C59
C74
C77
C78
D5
D6
L703
L705
L706
L707
L708
L709
CN70 1
L10
L11
U11
IC3
CN08
JR0
JR70 1
R1
R10
R11
R16
R19
R2
R23
R3
R4
R46
R50
R52
R53
R55
R56
R57
R63
R64
R65
R66
R67
R7
R701
R702
R703
R704
R705
R706
R707
R708
R709
R710
R711
R712
R713
R714
R715
R716
R717
R718
R719
R720
R721
R722
R723
R724
R725
R727
R728
R729
R730
R731
R732
R733
R734
R735
R736
R737
R738
R739
R740
R741
R742
R743
R744
R745
R746
R747
R748
R749
R750 R751 R752R753
R756
R757
R758
R759
R760
R761
R762
R763
R764
R765
R766
R767
R768
R769
R770
R771
R772
R773
R774
R775
R776
R777
R778
R779
R780
R781
R782
R783
R8
R823
R824
R825
R826
R827
R828
R829
R51
R54
R20
R21
R22
R48
R49
R13
R14
CN4
IC707
IC4
IC6
IC701
IC703
X702
R15
R30
C729
C736
X701
R31
R32
R33
R34
R35
R36
C784
C2
C5
C1
J2 1 5
IC1
Q220
C3
C4
R17
R18
R25
R27
R5
R6
R9
CN1B
Q1
R12
R24
R26
R830
R28
R29
R37
JP108
1V5
8V
BCLK
DATA
GND
LRCLK
MCLK
SPDIF
J2 2 0
J1
Test Point