NI sbRIO-960x/962x/963x OEM Instructions & Specifications 24 ni.com
FPGA_CONF
The FPGA_CONF signal asserts high when the FPGA has been
programmed. When the FPGA is unconfigured the signal is floating. A
pulldown resistor is required when using this signal to ensure it returns to
ground.
3.3 V Digital I/O
The NI sbRIO device provides 3.3 V digital I/O via the RIO Mezzanine
Card connector and the 50-pin IDC headers. The following sections
provide figures and specifications for a single DIO channel on each
connector.
3.3 V DIO on RMC Connector
Figure 19. Circuitry of One 3.3 V DIO Channel on the RIO Mezzanine Card Connector
The NI sbRIO device is tested with all DIO channels driving ±3 mA DC
loads. DIO lines are floating before and during FPGA configuration. To
ensure startup values, place pull-up or pull-down resistors on a RIO
Mezzanine Card. The DIO channels on the NI sbRIO device are routed with
a 55 Ω characteristic trace impedance. Route all RIO Mezzanine Cards
with a similar impedance to ensure the best signal quality. Refer to 3.3 V
Digital I/O on RIO Mezzanine Card Connector in the Specifications section
for the logic levels.
3.3 V DIO on IDC Header
Figure 20. Circuitry of One 3.3 V DIO Channel on the IDC Header
The NI sbRIO device is tested with all DIO channels driving ±3 mA DC
loads. DIO lines are floating before and during FPGA configuration. To
ensure startup values, place pull-up or pull-down resistors on a RIO
Mezzanine Card. The DIO channels on the NI sbRIO device are routed with
Xilinx Spartan-6 FPGA
RMC Connector
33 Ω
Xilinx Spartan-6 FPGA
IDC Header
49.9 Ω
Bus
Switch
16.9 Ω
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