National Instruments sbRIO-9605 - Page 23

© National Instruments 23 NI sbRIO-960x/962x/963x OEM Instructions & Specifications
RMC Power Requirements
The RIO Mezzanine Card connector provides power on six pins. The 5 V
rail consists of pins 54, 60, 66, and 72, and is the main source of power to
a RIO Mezzanine Card. The FPGA_VIO rail consists of pins 234 and 240,
and is used to supply I/O power and determine I/O levels for the FPGA I/O
pins.
Table 4 lists the rail requirements for each of the rails on a RIO Mezzanine
Card connector.
RIO Mezzanine Cards should not source any current onto any of the power
pins and should be able to tolerate 5 V and FPGA_VIO coming up in any
order.
RMC VBAT
The NI sbRIO device implements an onboard real-time clock (RTC) to
keep track of absolute time. The RMC connector provides a VBAT line to
power the RTC. Without a battery, absolute time will be reset during a
power cycle. Batteries connected to VBAT must have a nominal output
between 3.0 V and 3.6 V, and a maximum output of 3.7 V. If VBAT is not
being used, leave it disconnected.
USB on RMC Connector
The USB pair on the RMC Connector has a 90 Ω differential trace
impedance. To ensure the best possible signal integrity, route the USB pair
with a similar trace impedance. If USB is not being used, leave it
disconnected.
RMC RST#
The RST# signal indicates that power provided through the RMC
Connector is valid. RST# is guaranteed to be asserted (active low) for at
least 1 ms when the controller is powered up or reset. There should be no
more than 30 pF on the RST# line of a RIO Mezzanine Card. This includes
the RMC Connector, traces, vias, and device pins. Refer to 3.3 V Digital
I/O on RIO Mezzanine Card Connector in the Specifications section for
output logic levels.
Table 4. NI RIO Mezzanine Card Rail Requirements
Voltage Tolerance Max Current Max Ripple and Noise
5 V +/– 5% 1.5 A 50 mV
FPGA_VIO (3.3 V) +/– 5% 0.33 A 50 mV