4-15
OEP-3 V1 (UC)
4-1-7. Sampling Clock Generation Block
This block generates a sampling clock, locks the phase to the “high” level of external and internal sync
signals, and distributes the clock to the DRAM control circuit or color adjustment circuit.
The clock frequency is 17.897725 MHz for NTSC and 17.734475 MHz for PAL.
The operation timing is shown below.
To Next Page
Loading...
