4-4
OEP-3 V1 (UC)
Capture mode
In this mode, a video input signal is converted from analog to digital and fetched into DRAM.
The flow of an image signal is as described below.
The video signal input from an analog signal processing block is converted from analog to digital as an
eight-bit digital signal. The converted video signal is converted from 8 bits to 32 bits and decimated (e.g.,
8.16 division) in a DRAM control circuit (CXD9111R: IC1001), and expanded in DRAM.
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