4-41
OEP-3 V1 (UC)
Remote 2 output
The control signal of a BUSY output signal is output by CPU (pin 93 of IC100) and driven using a buffer
(IC404).
Remote 3 input
The remote control (FS-30) input signal connected to connector CN2 on the IF-767 board is processed by
IC407 and input through a data bus to CPU. The timing pulse of a data input signal is output by IC110.
Remote 3 output
The control signal of a VD output signal is output by the VPR-63 board and driven using an inverter
(IC401).
The control signal of a Light output signal is output by the VPR-63 board and driven using a buffer
(IC404).
The control signal of a Busy output signal is output by the CPU (pin 93 of IC100) and driven using a
buffer (IC404).
Antenna drive circuit
CUP communicates with antenna board (AN-15) control block IC2 (CXD8753Q) using serial data. In the
standby state, an AN_RESET signal is set low to stop the antenna circuit operation.
Signal line name I/O Description
AN_TXD (TP10) Output Communication data (CPU → IC)
AN_RXD (TP6) Input Communication data (IC → CPU)
AN_SCK (TP8) Output Communication clock (SY → IC)
AN_REQ (TP7) Output Send request (SY → IC) L:active
AN_SINT (TP9) Input Send request (IC → SY) L:active
AN_RESET (TP5) Output Reset (SY → IC) L:active
Communication format
System Clock synchronous system
Data length 8 bits
Remarks:
. “CHECK RIBBON 80” is displayed even if an ink ribbon is defective.
. “CHECK RIBBON” is displayed when the ribbon that cannot be used in a model is used.
. The 12 V system on the SY-282 board is used only in an antenna drive circuit.
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