Panasonic TH-55CX700M - Block Diagram; Main Block Diagram

TH-55CX700M TH-60CX700M
36
9 Block Diagram
9.1. Main Block Diagram
S3.3
YPbP r
L/R in x 2
OPT
Ana lo g AV
Y
Pb
Pr
R
L
Op tical O U T
S 5/ S 3.3
S3.3
eMMC
32Gbit
De bu g
Co nn ector
A-SW
(T hru)
V-SW
HD M I
R x
MUX
x4
ADC
[3:1 ]
Analog V ide o
Proc ess or
ADC
D A C
ADC
Pr e
Processo r
A-C h ip
SPDI F
SW
D-Chip
Trans P o rt De m u x
DDR 3
Controller
SD -IF
Audio
D SP
STB3.3
AV
Decoder
EASTER
S erial
S erial1
IIC
STM-I IC
Serial
ST M- Se ria l0
24 MHz
CLK
G EN
SOUND _VC C
LVD S -Tx/
mi ni-LVDS -Tx
V-b y-On e
T-CO N
DDR 1 .5
ATV
Decode r
DVB -C
Decode r
US B
IF
x4
ETHER -IF
FEA INP
FEAINN
Internal CI
controller
Lo w -IF
DM D
W ired O R
I2 S (MCLK /LRCLK /BCLK /S DAT[1:0])
X RST/#S OS/#AMP_MU T E
DDR3
4G bit
ADC
[0 ]
TV Decode r
SAW
FLT
Di gital CVBS
DVB -T
Decode r
AT SC/Q AM
Decode r
Di gital SIF
M IB
(IPNR)
M ain
Sub
O S D
1, 2 ,3
cursor
E xternal Video(Ana log)
E xte rna l V ide o(HDM I)
De c video
x80
TVE
OSD
5
VD A C
PQ
MJ C
(FR C ,
3D )
Scale r
Dec Audio
ADx8
B2R
SPI -IF
S CL K
S DI
S DO
C E#1
S1.5
S3.3
S1.0
IIC
BE_IIC0
BE_IIC1
BE_IIC2
S1.8
I2S AMP
YD A176 -QZ
(YAM AHA)
STB3.3
EEP
16 k
< EEPR O M_WP
STB-IIC
For uP
IFAGC0
IF0
(TU _Para_ T S1)
AR M
XRST
PO W ER _ DE T
< TV_SOS
AMP/HP MUTE
MO N ITO ROU T M UT E
F15 V
STB5V
Analog
ASIC
OVP
SOS
Safety
Circuit
< M ON _MUTE
< SP _HP_M UTE
PWM
A
PWM_ENB >
PWMOUT
Common-Res et
Pa rago n
Reset
Circuit
S DC L K,SDC M D ,
SDD AT[3:0],SDCD ,SDWP
SD XC
/UHS-I
S3.3
REG
S5
S3.3/ 1. 8
UHS -I
SDV O LC
USB2.0
(Port 0)
USB2.0
(port1 )
USB3.0
(Port 2)
USB 2.0
(Port 3 )
DDR3
4G bit
DDR3
4G bit
DDR3
4Gbit
DDR3
x1 6
4G bit
DDR3 1866 4Gb x5
M MCCL K
MMCCM D
XER ST
MMCD AT 0-7
eMMC-IF
S1.05
M AIN
SUB
SPI -IF
Rx0
Rx1
Rx2
R x3
S 3.3/ S1.2
DVB- T 2/T /C
DVB-S/S2
DE MOD
1
< FE_XRST
B E- IIC
41M Hz
TU_Serial_ T S1
(TU _Para_ T S1)
IFAG C 1
IF1
TU -IIC 1
S 3.3/ S1.8
TUNE R
IFAG C0
EX T _IF A GC1
F
T U-IIC1
IF0
TU_Serial_ TS1 / TU_Se rial_ T S1_J P
DDC* > S T M
HPD* < ST M
HD M I_5 V_DE T * > S TM
DDC* >
STM
HPD* < STM
HD MI_5V _D ET* > STM
HPD* < ST M
HD M I_5V _DE T* > STM
DDC* > S T M
I2S
S3 .3 / S1 .1
HD M I
SW
MN864
77 8
< HD M I_X RST
BE- IIC
27 MH z
HD M I2. 0
< HD M I_IR Q
HDM I1
HDM I2
HDM I3
Rx0
Rx1
R2R
HD MI1.4
HD M I1.4
HD M I2.0
HD M I2.0
ARC OU T
Lch:10 W
Rch:10 W
Vb yO ne 8 Lane (Video )
V byOne 4 Lane (OSD)
Panel
(Tcon)
N T 72324
SP I-FLASH
N T K3.3V
16 Mb
DDR 3
DDR 3
1G 4
NT1.5V
DDR 3
DDR 3
NT_PA NE L_VCC _ON
FR_ GPA_0 (SP I_CS )
FR _G PA_ 1 (SP I_ CL K)
FR_ G PA_ 2 ( SP I_DI)
FR_ G PA_ 3 (SP I_ DO )
12MHz
DISPEN
LOGO_ON ,BL_ON
NT _X RS T
PNL 3D ON
PN L TEST O N
PC ID _EN
3D_ON, BL_S OS
P
LD
TV_S U B_ O N
GPIOx8
NT_BL_PWM1-8
KE YSCAN/P O W ER-KEY
ETHER
10 /10 0M
STB 5.3
S5
S3.3
24 MHz
S3.3
USB -HU B
GL850 G
IEEE 802. 11 n
W ireless UN IT
HUB _XRS T <
USB 2.0 -IF
USB
Po w e r SW
S5
USB 2.0 -IF
BT Modul e
HDD-US B
Po w er SW
USB 3.0 -IF
For Wake up On Wireless (Euro)
WOW_ON_IRQ <
< PH Y_PWR_ON
> WOW_OV P
USB*VBUS >
< OVC U R*
USB
Po wer SW
S5
USB*VBUS >
< OVC UR*
USB
Po w er SW
S5
USB*VBUS >
< OVC UR*
USB -1
(C amera)
USB -2
USB -3
(3.0 HDD )
IFAG C1
IF1