Philips S37SD-YD02 - Page 41

Block Diagrams, Test Point Overview, and Waveforms
EN 41SDI PDP 6.
Figure 6-3 Block diagram (42" SD v3)
Figure 6-4 Block diagram (42" SD v4)
F_14991_032.eps
030805
F_14991_002.eps
180705
ASIC
SPS- S101
128K
DDR
128K
DDR
ASIC
SPS- S101
128K
DDR
128K
DDR
LVDS
INPUT
(Clock,
RGB,Data,
V-, H-sync,
DE)
I2C
Interface
signal
X, Y
FET
Control
TCP
CLK, DATA
Control
Logic Main Block Diagram