LPWA Module Series
BG77 Hardware Design
BG77_Hardware_Design 16 / 76
3.1. Pin Assignment
The following figure shows the pin assignment of BG77.
38
38 RTS 77 AP_READY
32 31 30 29 28 27 26
53545556
1
2
3
4
5
6
7
8
9
40
39
37
36
35
34
33
57
58
59
60
61
62
63
73
74
75
76
77
78
89
88
87
86
85 94
93
92
91
90
79
80
81
82
83
84
71
70
69
68
67
66
65
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
72
41 42
64
43 44
10 11 12 13 14 15 16
60 DBG_TXD
1 GP IO1
5 I2C_SDA
UART
33 GP IO2
34 PCM_DOUT
35 PCM_SY NC
36 GNSS_TXD
37 I2C_SCL
39 C TS
40 SP I_M OSI
ANT GND
26
ANT_M AIN
32
ANT_GNSS
57 GP IO3
61 DBG_RXD
62 DTR
63 SP I_CS
78 STA TUS
76 RI
87 USB_BO OT
I2C SP I
DCD 90
NETLIGHT 79
ADC1
18
10
USB_DM
11
USB_DP
12
USB_VBUS
4)
13
USIM_CLK
14
USIM_DATA
15
USIM_RST
16
USIM_VDD
44
USIM_DET
42
USB_VDDA_3P3
64
EX T_PW R_EN
ADC0 17
VBAT 19
VBAT 20
VDD_EXT 21
USBUSIM
PO WER
2 PCM_DIN
3 PCM_CLK
4 GNSS_RXD
6 RXD
7 TXD
8 SP I_MISO
9 SP I_CLK
USB PCM RESE RVED OTHERS
41
W_DISA BLE #
RESE T_N
45
PWRKEY
46
USIM_GND 65
72
PO N_TRIG
GR FC2 94
GR FC1 83
Figure 2: Pin Assignment (Top View)
1. PWRKEY output voltage is 1.5V because of the voltage drop inside the Qualcomm chipset. Due to
platform limitations, the chipset has integrated the reset function into PWRKEY. Therefore, PWRKEY
should never be pulled down to GND permanently.
2. RESET_N is multiplexed from PWRKEY
.
NOTES
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