Quectel BG77 - Antenna Interfaces; Main Antenna Interface; Pin Definition and Frequency

LPWA Module Series
BG77 Hardware Design
BG77_Hardware_Design 48 / 76
Table 24: Pin Definition of SPI Interface
1. SPI_MOSI cannot be pulled up before the module powers up.
2. The module provides 1.8V SPI interface. A level translator should be used between the module and
the host if customers’ application is equipped with a 3.3V processor or device interface.
3. “*” means under development.
3.19. GPIO Interfaces*
The module provides three general-purpose input and output (GPIO) interfaces. AT+QCFG=
"gpio"*
command can be used to configure corresponding GPIO pin’s status. For more details about the AT
command, please refer to document [2].
Table 25: Pin Definition of GPIO Interfaces
The following table describes the characteristics of GPIO interfaces.
Table 26: Logic Levels of GPIO Interfaces
Pin Name Pin No. I/O Description Comment
SPI_MOSI 40 DO SPI master-out slave-in
BOOT_CONFIG.
Do not pull it up before startup.
1.8V power domain
SPI_MISO 8 DI SPI master-in slave-out 1.8V power domain
SPI_CS_N 63 DO SPI chip select 1.8V power domain
SPI_CLK 9 DO SPI clock 1.8V power domain
Pin Name Pin No. Description
GPIO1 1 General-purpose input and output interface
GPIO2 33 General purpose input and output interface
GPIO3 57 General purpose input and output interface
Parameter Min. Max. Unit
NOTES