Quectel BG95 Series

LPWA Module Series
BG95 Hardware Design
BG95_Hardware_Design 45 / 80
Table 13: Pin Definition of Debug UART Interface
Table 14: Pin Definition of GNSS UART Interface
The logic levels of UART interfaces are described in the following table.
Table 15: Logic Levels of Digital I/O
The module provides 1.8V UART interface. A level translator should be used if customers’ application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments
is recommended. The following figure shows a reference design of the Main UART interface:
Pin Name Pin No. I/O Description Comment
DBG_RXD 22 DI Receive data 1.8V power domain
DBG_TXD 23 DO Transmit data 1.8V power domain
Pin Name Pin No. I/O Description Comment
GNSS_UART_TXD 27 DO Transmit data 1.8V power domain
GNSS_UART_RXD 28 DI Receive data 1.8V power domain
Parameter Min. Max. Unit
V
IL
-0.3 0.6 V
V
IH
1.2 2.0 V
V
OL
0 0.45 V
V
OH
1.35 1.8 V