Quectel EM05-G - Page 34

LTE Standard Module Series
EM05-G Hardware Design
EM05-G_Hardware_Design 33 / 69
Host Module
RESET#
PMIC
GPIO
67
Reset pulse
150–460 ms
Q1
NPN
R3
100k
R2
1k
Figure 12: Reference Circuit of RESET# with NPN Driver Circuit
Module
RESET#
Reset
Logic
67
150-460 ms
S1
TVS
33 pF
C1
Note:
The capacitor C1 is recommended to be less than 47 pF.
Figure 13: Reference Circuit of RESET# by Using Button