Renesas RA Family RA4 Quick Design Guide
R01AN5988EU0100 Rev.1.00 Page 35 of 51
Jul.21.21
Table 14. PRCR Protection Bits
• Registers related to the Clock Generation Circuit:
SCKDIVCR, SCKDIVCR2, SCKSCR, PLLCCR, PLLCR, BCKCR, MOSCCR,
HOCOCR, MOCOCR, CKOCR, TRCKCR, OSTDCR, OSTDSR, EBCKOCR,
SDCKOCR, MOCOUTCR, HOCOUTCR, MOSCWTCR, MOMCR, SOSCCR,
SOMCR, LOCOCR, LOCOUTCR, HOCOWTCR, FLLCR1, FLLCR2
• Registers related to the low power modes:
SBYCR, SNZCR, SNZEDCR, SNZREQCR, OPCCR, SOPCCR, DPSBYCR,
DPSIER0-3, DPSIFR0-3, DPSIEGR0-2, SYOCDCR, STCONR
• Registers related to the battery backup function:
VBTBKRn (n = 0 to 511), VBTICTLR
• Registers related to the LVD:
LVD1CR1, LVD1SR, LVD2CR1, LVD2SR, LVCMPCR, LVDLVLR, LVD1CR0,
• Registers related to the security function:
CGFSAR, RSTSAR, LPMSAR, LVDSAR, BBFSAR, DPFSAR, CSAR, SRAMSAR,
STBRAMSAR, DTCSAR, DMACSAR, ICUSARx, BUSSARx, MMPUSARx, TZFSAR,
CPUDSAR, FSAR, PSARx, MSSAR, PmSAR, ELCSARx
These bits control write access to the PRCR register. To modify the
PRCR register, write A5h to the eight higher-order bits and the wanted
value to the eight lower-order bits as a 16-bit unit.
Note 1. Not present on Arm Cortex-M4 devices.
The Renesas FSP provides two APIs (R_BSP_RegisterProtectEnable and R_BSP_RegisterProtectDisable)
to enable and disable Register Write Protection respectively.
10. I/O Port Configuration
The “I/O Ports” section of the Hardware User’s Manual describes exact pin configurations based on
peripheral selection and other register settings. Some general information is listed as follows.
It is important to note that after a reset, each pin will be in the default state for that pin. Most pins are not
configured until the application code starts to execute. There may be a small period where some pins may be
in an undesirable state. This will be true regardless of what configuration method is used. The user should
consider the impact this may have for each application, including the effect this may have on other system
features.
The IO Port Configuration may be set using either direct write to registers or using FSP Pin Configuration.
10.1 Multifunction Pin Selection Design Strategies
Most pins on the RA4 Series of MCUs can be configured from a selection of multiple peripheral functions.
Tools, such as the pin configurator in FSP, are available from Renesas to assist with assigning pins for each
peripheral function. When several peripheral functions are needed, use the following design strategies to
help with pin selection.
• Assign peripheral functions with only one pin option first. For example, there is only one pin option for
each Trace Data signal in the debug function. When this function is needed, assign these pins first.
• Assign peripheral functions with limited pin options next. For example, devices that support the QSPI
peripheral typically only have two pin options for each QSPI signal.
• Assign peripheral functions with multiple pin options last. One example would be the Serial
Communications Interface (SCI) which typically has many available pin options.
• Some peripheral function pin options are interchangeable, while others must be assigned in logical
groups. For example, the IIC peripheral has some pins with the suffix “_A” while others have the suffix
“_B” in the signal name. Pins should be selected to have the same suffix for the peripheral function. Other
peripheral functions do not have this type of suffix, and pins may be assigned interchangeably, such as
the USB_VBUSEN signal for the USBFS peripheral function. Also see Section 15.3 in this document.
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