Renesas RH850 Series Application Note

RH850 Series CAN Transmit Procedure (CAN FD Mode)
R01AN6029EJ0100 Rev.1.0 Page
41
of 42
May 10, 2017
Table 9-2 CAN-related Interrupt Sources
【Note】 1. The interrupt request flag and interrupt enable bit in the interrupt function are not described.
For details, refer to the interrupt chapter in the hardware chapter of each user's manual.
2. Settings of the RFIGCV[2:0] bit of the RFCCx register
⎯ ・When a message is stored up to 1/8 in the receive FIFO buffer*
⎯ ・When a message is stored up to 2/8 in the receive FIFO buffer
⎯ ・When a message is stored up to 3/8 in the receive FIFO buffer*
⎯ ・When a message is stored up to 4/8 in the receive FIFO buffer
⎯ ・When a message is stored up to 5/8 in the receive FIFO buffer*
⎯ ・When a message is stored up to 6/8 in the receive FIFO buffer
⎯ ・When a message is stored up to 7/8 in the receive FIFO buffer*
⎯ ・When the receive FIFO buffer is full
* Do not set if the number of buffers in the receive FIFO buffer is set to 4 messages (the RFDC [2:0] bit of
the RFCCx register is "B'001").
3. Settings of the RFIGCV[2:0] bit of the CFCCk register
⎯ ・When a message is stored up to 1/8 in the transmit/receive FIFO buffer*
⎯ ・When a message is stored up to 2/8 in the transmit/receive FIFO buffer
⎯ ・When a message is stored up to 3/8 in the transmit/receive FIFO buffer*
⎯ ・When a message is stored up to 4/8 in the transmit/receive FIFO buffer
⎯ ・When a message is stored up to 5/8 in the transmit/receive FIFO buffer*
⎯ ・When a message is stored up to 6/8 in the transmit/receive FIFO buffer
⎯ ・When a message is stored up to 7/8 in the transmit/receive FIFO buffer*
⎯ ・When the transmit/receive FIFO buffer is full
※Do not set if the number of buffers in the transmit/receive FIFO buffer is set to 4 messages (the CFDC [2:
0] bit of the CFCCk register is “B’001”).
4. An interrupt is generated when any one of the following is detected.
⎯ ・The ADERR flag in the CmERFL register is “1”, and a form error is detected by ACK delimiter.
⎯ ・The B0ERR flag in the CmERFLL register is “1”, and a recessive is detected despite sending a
dominant.
⎯ ・The B1DRR flag in the CmERFL register is “1”,L and a dominant is detected despite sending a
recessive.
⎯ ・The CERR flag in the CmERFL register is “1”,L and a CRC error is detected.
⎯ ・The AERR flag in the CmERFLL register is “1”,L and an ACK error is detected.
⎯ ・The FERR flag in the CmERFLL register is “1”,L and a form error is detected.
⎯ ・The SERR flag in the CmERFLL register is “1”,L and a stuff error is detected.
5. If you return from the bus-off state by the following methods before 11 consecutive recessive bits 128 times
are detected, no interrupt will be generated (the BORF flag will not be "1").
⎯ ・When the CHMDC [1: 0] bit of the CmCTR register is set to "B'01" (channel reset mode)
⎯ ・When the RTBO bit of the CmCTR register is set to "1" (forced recovery from bus off)
⎯ ・When the BOM [1: 0] bit of the CmCTR register is set to "B'01" (transition to channel standby
mode when bus off starts)
⎯ ・When the BOM [1: 0] bit is “B'11” (transition to channel standby mode at the request of the
program during bus off) and the CHMDC [1: 0] bit is set to “B'10” (channel standby mode) before
detecting 11 consecutive recessive bits 128 times.

Renesas RH850 Series Specifications

General

Core	RH850
Operating Voltage	2.7V to 5.5V
Package Options	LQFP, BGA
Communication Interfaces	CAN, LIN, FlexRay, Ethernet, SPI, I2C, UART
Target Applications	Automotive, Industrial
Timers	Multiple timers
ADC	12-bit, 10-bit
Security Features	Hardware Security Module (HSM)
Safety Features	Memory Protection